PSoC™ Mixed-Signal Array
Preliminary Data Sheet
FAN Controller
CG6457AM and CG6462AM
Features
■ Excellent for Fan Control Applications
■ Flexible On-Chip Memory
■ Precision, Programmable Clocking
■ Internal ±3.5% 24 MHz Oscillator
■ 4K Flash Program Storage
■ 256 Bytes SRAM Data Storage
■ In-System Serial Programming (ISSP™)
■ Partial Flash Updates
■ Powerful Harvard Architecture Processor
■ M8C Processor Speeds to 12 MHz
■ Low Power at High Speed
■ Internal Oscillator for Watchdog and Sleep
■ Programmable Pin Configurations
■ 25 mA Drive on All GPIO
■ 4.75V to 5.25V Operating Voltage
■ Flexible Protection Modes
■ Extended Temperature Range:
■ Pull Up, Pull Down, High Z, Strong, or Open
-40°C to +125°C
Drain Drive Modes on All GPIO
■ Complete Development Tools
■ Advanced Peripherals (PSoC Blocks)
■ 4 Analog Type “E” PSoC Blocks Provide:
- 2 Comparators with DAC Refs
■ Up to 8 Analog Inputs on GPIO
■ Configurable Interrupt on All GPIO
■ Free Development Software
(PSoC™ Designer)
■ Full-Featured, In-Circuit Emulator and
Programmer
■ Additional System Resources
- Single or Dual 8-Bit 8:1 ADC
■ Full Speed Emulation
■ I2C™ Master, Slave and Multi-Master to
■ 4 Digital PSoC Blocks Provide:
- 8- to 32-Bit Timers, Counters, and PWMs
- CRC and PRS Modules
■ Complex Breakpoint Structure
■ 128 Bytes Trace Memory
400 kHz
■ Watchdog and Sleep Timers
- Full-Duplex UART, SPI™ Master or Slave
- Connectable to All GPIO Pins
■ User-Configurable Low Voltage Detection
■ Integrated Supervisory Circuit
■ Complex Peripherals by Combining Blocks
■ On-Chip Precision Voltage Reference
PSoC™ Functional Overview
Port 1 Port 0
PSoC
The PSoC™ family consists of many Mixed-Signal Array with
On-Chip Controller devices. These devices are designed to
replace multiple traditional MCU-based system components
with one, low cost single-chip programmable component. A
PSoC device includes configurable blocks of analog and digital
logic, as well as programmable interconnect. This architecture
allows the user to create customized peripheral configurations,
to match the requirements of each individual application. Addi-
tionally, a fast CPU, Flash program memory, SRAM data mem-
ory, and configurable IO are included in a range of convenient
pinouts.
CORE
SystemBus
Global Digital Interconnect
Global Analog Interconnect
Flash
CPUCore
SROM
SRAM
Sleep and
Watchdog
Interrupt
Controller
(M8C)
Clock Sources
The PSoC architecture, as illustrated on the left, is comprised of
four main areas: the Core, the System Resources, the Digital
System, and the Analog System. Configurable global bus
resources allow all the device resources to be combined into a
complete custom system. Each PSoC device includes four digi-
tal blocks. Depending on the PSoC package, up to two analog
comparators and up to 16 general purpose IO (GPIO) are also
included. The GPIO provide access to the global digital and
analog interconnects.
(Includes IMO and ILO)
DIGITAL SYSTEM
ANALOG SYSTEM
Analog
Ref.
Analog
PSoC Block
Array
Digital
PSoC Block
Array
The PSoC Core
The PSoC Core is a powerful engine that supports a rich
instruction set. It encompasses SRAM for data storage, an
interrupt controller, sleep and watchdog timers, and IMO (inter-
nal main oscillator) and ILO (internal low speed oscillator). The
POR and LVD
System Resets
Internal
Voltage
Ref.
Digital
I2C
Clocks
SYSTEM RESOURCES
May 24, 2005
© Cypress Semiconductor Corp. 2005 — Document No. 001-00353 Rev. **
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