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C9870GT

更新时间: 2024-02-27 04:56:55
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 晶体时钟发生器微控制器和处理器外围集成电路光电二极管
页数 文件大小 规格书
25页 173K
描述
High Performance Pentium? 4 Clock Synthesizer

C9870GT 技术参数

生命周期:Obsolete零件包装代码:SSOP
包装说明:SSOP,针数:56
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.84
JESD-30 代码:R-PDSO-G56长度:18.415 mm
端子数量:56最高工作温度:70 °C
最低工作温度:最大输出时钟频率:200 MHz
封装主体材料:PLASTIC/EPOXY封装代码:SSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, SHRINK PITCH
主时钟/晶体标称频率:14.318 MHz认证状态:Not Qualified
座面最大高度:2.794 mm最大供电电压:3.465 V
最小供电电压:3.135 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子形式:GULL WING
端子节距:0.635 mm端子位置:DUAL
宽度:7.5057 mmuPs/uCs/外围集成电路类型:CLOCK GENERATOR, PROCESSOR SPECIFIC
Base Number Matches:1

C9870GT 数据手册

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Approved Product  
C9870G  
High Performance Pentium® 4 Clock Synthesizer  
3 Differential CPU Clocks  
Product Features  
SMBus Support with Read-back Capabilities  
Spread Spectrum EMI Reduction  
Dial-a-Frequency™ Features  
Dial-a-dB™ Features  
Supports Pentium® 4 Type CPUs  
3.3 Volt Power Supply  
10 Copies of PCI Clocks  
56 Pin SSOP and TSSOP Package  
Frequency Table  
S2  
S1 S0 CPU  
(0:2)  
3V66  
66BUFF(0:2)/  
3V66(0:4)  
66IN  
66IN/  
3V66-5  
66MHz clock input  
66MHz clock input  
66MHz clock input  
66MHZ clock input  
PCI_F  
PCI  
REF  
USB/  
DOT  
48M  
48M  
48M  
48M  
48M  
48M  
48M  
48M  
Hi-Z  
1
1
1
1
0
0
0
0
M
M
M
M
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
66M  
100M  
200M  
133M  
66M  
100M  
200M  
133M  
Hi-Z  
66M  
66M  
66M  
66M  
66M  
66M  
66M  
66M  
Hi-Z  
66IN/2  
66IN/2  
66IN/2  
66IN/2  
33 M  
33 M  
33 M  
33 M  
Hi-Z  
14.318M  
14.318M  
14.318M  
14.318M  
14.318M  
14.318M  
14.318M  
14.318M  
Hi-Z  
66IN  
66IN  
66IN  
66M  
66M  
66M  
66M  
Hi-Z  
66M  
66M  
66M  
66M  
Hi-Z  
TCLK/4  
50M  
55.5M  
TCLK/2  
150M  
166.6M  
TCLK/4  
50M  
55.5M  
TCLK/4  
50M  
55.5M  
TCLK/8  
25M  
27.7M  
TCLK  
14.318M  
14.318M  
TCLK/2  
48M  
48M  
Note: TCLK is a test clock over driven on the XTAL_IN input during test mode. M= driven to a level between 1.0 and 1.8 Volts  
If the S2 pin is at a M level during power up, a 0 state will be latched into the devices internal state register.  
Block Diagram  
Pin Configuration  
XIN  
XOUT  
REF  
VDD  
XIN  
XOUT  
1
2
3
4
5
6
7
8
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
REF  
S1  
S0  
CPU_STP#  
CPU0  
CPU/0  
VDD  
CPU1  
CPU/1  
VSS  
VDD  
CPU2  
CPU/2  
MULT0  
IREF  
VSSIREF  
S2  
48MUSB  
48MDOT  
VDD  
CPU(0:2)  
CPU/(0:2)  
VSS  
PLL1  
PCIF0  
PCIF1  
PCIF2  
VDD  
VSS  
PCI0  
PCI1  
PCI2  
PCI3  
VDD  
VSS  
PCI4  
PCI5  
PCI6  
VDD  
VSS  
CPU_STP#  
IREF  
VSSIREF  
9
3V66_0  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
S(0:2)  
3V66_1/VCH  
MULT0  
VTT_PG#  
PCI_STP#  
/2  
PCI(0:6)  
PCI_F(0:2)  
48M USB  
48M DOT  
PLL2  
PD#  
66B0/3V66_2  
66B1/3V66_3  
66B2/3V66_4  
66IN/3V66_5  
PD#  
VSS  
WD  
Logic  
3V66_1/VCH  
PCI_STP#  
3V66_0  
VDD  
VSS  
SCLK  
I2C  
Logic  
SDATA  
SCLK  
VDDA  
VSSA  
VTT_PG#  
66B[0:2]/3V66[2:4]  
66IN/3V66-5  
Power  
Up Logic  
VDDA  
SDATA  
Cypress Semiconductor Corporation  
http://www.cypress.com  
Document#: 38-07108 Rev. *A  
12/26/2002  
Page 1 of 25  

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