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C9851BT

更新时间: 2024-01-06 05:41:10
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 晶体时钟发生器微控制器和处理器外围集成电路光电二极管服务器
页数 文件大小 规格书
14页 125K
描述
Clock Generator for Pentium III Server and Workstation Applications

C9851BT 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:TSSOP包装说明:TSSOP-48
针数:48Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.92JESD-30 代码:R-PDSO-G48
JESD-609代码:e0长度:12.5 mm
端子数量:48最高工作温度:70 °C
最低工作温度:最大输出时钟频率:200 MHz
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP48,.3,20封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):NOT SPECIFIED
电源:3.3 V主时钟/晶体标称频率:14.318 MHz
认证状态:Not Qualified座面最大高度:1.2 mm
子类别:Clock Generators最大压摆率:30 mA
最大供电电压:3.465 V最小供电电压:3.135 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.5 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:6.1 mm
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, PROCESSOR SPECIFICBase Number Matches:1

C9851BT 数据手册

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PRELIMINARY  
C9851  
Clock Generator for Pentium III Server and Workstation Applications  
Product Features  
Product Description  
This device provides the necessary clocks for a  
differential host bus system in multi-processor servers  
and workstations. It also generates a 66.6MHz hub  
clock for interfacing with a complimentary part, the  
Cypress B9852. The 2 Mref clock outputs are 180  
degrees out of phase and are used for interfacing with  
the Direct Rambus Clock Generator (DRCG), C9820,  
C9821, or C9822. This device integrates the Cypress  
spread spectrum technology for optimum EMI  
reduction.  
Six pairs of current referenced differential clocks  
Two 3V 180° displaced Mref clocks for DRCG  
One 66.6 MHz reference output  
One 14.318 MHz reference output  
Select logic for Differential Swing Control, Test  
mode, Hi-Z, Power-down, Spread spectrum, and  
limited frequency select  
Cypress Spread Spectrum for EMI reduction  
48 Pin SSOP Package  
Frequency Selection Table  
SEL 100/133 SELA SELB  
CPU(1:6), CPU#(1:6)  
3VMref,  
3V66  
REF  
3Vmref_b  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
100 MHz  
100 MHz  
200 MHz  
Hi-Z  
133.3 MHz  
25 MHz  
200 MHz  
REF/2  
50 MHz  
Low  
50 MHz  
Hi-Z  
66.67 MHz  
50 MHz  
66.7 MHz  
REF/4  
66.67 MHz  
Low  
66.67 MHz  
Hi-Z  
66.67 MHz  
66.67 MHz  
66.67 MHz  
REF  
14.318 MHz  
Low  
14.318 MHz  
Hi-Z  
14.318 MHz  
14.318 MHz  
14.318 MHz  
REF  
Table 1  
Block Diagram  
Pin Configuration  
VSSR  
Ref  
VDDR  
XIN  
XOUT  
VSSR  
1
2
3
4
5
6
7
8
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
VDD  
VSS  
VDDR  
REF  
XIN  
OSC  
VDDC  
CPU1  
CPU1#  
VSSC  
CPU2  
CPU2#  
VDDC  
CPU3  
CPU3#  
VSSC  
CPU4  
CPU4#  
VDDC  
CPU5  
CPU5#  
VSSC  
CPU6  
CPU6#  
VDDC  
I_Ref  
VSSR  
XOUT  
VDDA  
VDDM  
3VMref  
3VMref_b  
VSSM  
VDD  
I_Ref  
VSSI  
I
MultSel(0:1)  
Control  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
CPU (1:6)  
CPU (1:6)#  
VDDM  
Spread#  
SelA  
VCO  
VSS  
VDDL  
3V66  
VSSL  
SelB  
SEL100/133  
3VMRef  
3VMRef_b  
VSSM  
SEL100/133  
MultSel0  
MultSel1  
VDDA  
VSSA  
SelA  
SelB  
Spread#  
PwrDwn#  
PwrDwn#  
VDDL  
3V66  
VSSL  
VSSA  
VDDA  
Cypress Semiconductor Corporation  
525 Los Coches St.  
Document#: 38-07068 Rev. **  
05/04/2001  
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571  
http://www.cypress.com  
Page 1 of 14  

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