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B9949 PDF预览

B9949

更新时间: 2024-01-17 00:14:36
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟
页数 文件大小 规格书
8页 66K
描述
3.3V 160-MHz 1:15 Clock Distribution Buffer

B9949 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:QFP包装说明:TQFP-52
针数:52Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.88
Is Samacsys:N系列:9949
输入调节:DIFFERENTIAL MUXJESD-30 代码:S-PQFP-G52
JESD-609代码:e0长度:10 mm
逻辑集成电路类型:LOW SKEW CLOCK DRIVER最大I(ol):0.02 A
湿度敏感等级:1功能数量:1
反相输出次数:端子数量:52
实输出次数:15最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:TQFP
封装等效代码:TQFP52,.47SQ,25封装形状:SQUARE
封装形式:FLATPACK, THIN PROFILE峰值回流温度(摄氏度):235
电源:3.3 VProp。Delay @ Nom-Sup:10.5 ns
传播延迟(tpd):10.5 ns认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.35 ns座面最大高度:1.2 mm
子类别:Clock Drivers最大供电电压 (Vsup):3.465 V
最小供电电压 (Vsup):3.135 V标称供电电压 (Vsup):3.3 V
表面贴装:YES温度等级:INDUSTRIAL
端子面层:TIN LEAD端子形式:GULL WING
端子节距:0.65 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:10 mm
Base Number Matches:1

B9949 数据手册

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B9949  
3.3V 160-MHz 1:15 Clock Distribution Buffer  
Features  
Description  
• 160MHz Clock Support  
The B9949 is a low-voltage clock distribution buffer with the  
capability to select either a differential LVPECL or LVC-  
MOS/LVTTL compatible input clocks. These clock sources  
can be used to provide for test clocks as well as the primary  
system clocks. All other control inputs are LVCMOS/LVTTL  
compatible. The 15 outputs are 3.3V LVCMOS or LVTTL com-  
patible and can drive two series terminated 50transmission  
lines. With this capability the B9949 has an effective fan-out of  
1:30.  
• LVPECL or LVCMOS/LVTTL Clock Input  
• LVCMOS/LVTTL Compatible Inputs  
• 15 Clock Outputs: Drive up to 30 Clock Lines  
• 1X and 1/2X Configurable Outputs  
• Output Three-state Control  
• 350 ps Maximum Output-to-Output Skew  
• Pin Compatible with MPC949  
The B9949 is capable of generating 1X and 1/2X signals from  
a 1X source. These signals are generated and retimed inter-  
nally to ensure minimal skew between the 1X and 1/2X sig-  
nals. SEL(A:D) inputs allow flexibility in selecting the ratio of  
1X to1/2X outputs.  
• Industrial Temp. Range: –40°C to +85°C  
• 52-Pin TQFP Package  
The B9949 outputs can also be three-stated via MR/OE# in-  
put. When MR/OE# is set HIGH, it resets the internal flip-flops  
and three-states the outputs.  
Block Diagram  
TCLK_SEL  
TCLK0 (LVTTL)  
0
/1  
/2  
0
1
TCLK1 (LVTTL)  
1
R
PECL_CLK  
PECL_CLK#  
0
2
QA0:1  
PCLK_SEL  
DSELA  
1
0
3
QB0:2  
1
DSELB  
DSELC  
0
4
QC0:3  
1
0
6
QD0:5  
1
DSELD  
MR/OE#  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
Document #: 38-07081 Rev. *C  
Revised December 21, 2002  

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