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B9947 PDF预览

B9947

更新时间: 2024-02-21 19:23:09
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟
页数 文件大小 规格书
5页 61K
描述
3.3V, 160-MHz, 1:9 Clock Distribution Buffer

B9947 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:QFP包装说明:TQFP-32
针数:32Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.91
Is Samacsys:N系列:9947
输入调节:MUXJESD-30 代码:S-PQFP-G32
JESD-609代码:e0长度:7 mm
逻辑集成电路类型:LOW SKEW CLOCK DRIVER最大I(ol):0.02 A
功能数量:1反相输出次数:
端子数量:32实输出次数:9
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:TQFP封装等效代码:TQFP32,.35SQ,32
封装形状:SQUARE封装形式:FLATPACK, THIN PROFILE
峰值回流温度(摄氏度):240电源:3.3 V
Prop。Delay @ Nom-Sup:9.25 ns传播延迟(tpd):9.25 ns
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.35 ns
座面最大高度:1.2 mm子类别:Clock Drivers
最大供电电压 (Vsup):3.63 V最小供电电压 (Vsup):2.97 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
温度等级:INDUSTRIAL端子面层:TIN LEAD
端子形式:GULL WING端子节距:0.8 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:7 mm最小 fmax:160 MHz
Base Number Matches:1

B9947 数据手册

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B9947  
3.3V, 160-MHz, 1:9 Clock Distribution Buffer  
Product Features  
Description  
• 160-MHz Clock Support  
• LVCMOS/LVTTL Compatible Inputs  
• 9 Clock Outputs: Drive up to 18 Clock Lines  
• Synchronous Output Enable  
• Output Three-state Control  
• 350-ps Maximum Output-to-Output Skew  
• Pin Compatible with MPC947  
• Industrial Temp. Range: –40°C to +85°C  
• 32-Pin TQFP Package  
The B9947 is a low-voltage clock distribution buffer with the  
capability to select one of two LVCMOS/LVTTL compatible  
clock inputs. The two clock sources can be used to provide for  
a test clock as well as the primary system clock. All other con-  
trol inputs are LVCMOS/LVTTL compatible. The nine outputs  
are 3.3V LVCMOS or LVTTL compatible and can drive two  
series terminated 50transmission lines. With this capability  
the B9947 has an effective fanout of 1:18. The outputs can  
also be three-stated via the three-state input TS#. Low out-  
put-to-output skews make the B9947 an ideal clock distribu-  
tion buffer for nested clock trees in the most demanding of  
synchronous systems.  
The B9947 also provides a synchronous output enable input  
for enabling or disabling the output clocks. Since this input is  
internally synchronized to the input clock, potential output  
glitching or runt pulse generation is eliminated.  
Block Diagram  
Pin Configuration  
VDD  
VDDC  
TCLK0  
0
1
9
Q0-Q8  
VSS  
TCLK_SEL  
TCLK0  
TCLK1  
SYNC_OE  
TS#  
1
2
3
4
5
6
7
8
24  
23  
22  
21  
VSS  
Q3  
VDDC  
Q4  
TCLK1  
TCLK_SEL  
SYNC_OE  
TS#  
B9947 20 VSS  
19  
18  
17  
Q5  
VDDC  
VSS  
VDD  
VSS  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
Document #: 38-07078 Rev. *C  
Revised December 22, 2002  

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