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B9940L PDF预览

B9940L

更新时间: 2024-01-29 09:40:04
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟
页数 文件大小 规格书
5页 185K
描述
2.5V or 3.3V, 200-MHz, 1:18 Clock Distribution Buffer

B9940L 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:QFP包装说明:LQFP-32
针数:32Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.91
其他特性:ALSO OPERATABLE AT 3.3V输入调节:DIFFERENTIAL MUX
JESD-30 代码:S-PQFP-G32JESD-609代码:e0
长度:7 mm逻辑集成电路类型:LOW SKEW CLOCK DRIVER
最大I(ol):0.02 A功能数量:1
反相输出次数:端子数量:32
实输出次数:18最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:LQFP封装等效代码:QFP32,.35SQ,32
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE
峰值回流温度(摄氏度):240电源:2.5/3.3 V
Prop。Delay @ Nom-Sup:5.2 ns传播延迟(tpd):5.2 ns
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.2 ns
座面最大高度:1.6 mm子类别:Clock Drivers
最大供电电压 (Vsup):2.625 V最小供电电压 (Vsup):2.375 V
标称供电电压 (Vsup):2.5 V表面贴装:YES
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.8 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:7 mmBase Number Matches:1

B9940L 数据手册

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B9940L  
2.5V or 3.3V, 200-MHz, 1:18 Clock Distribution Buffer  
Features  
Description  
• 200-MHz clock support  
The B9940L is a low-voltage clock distribution buffer with the  
capability to select either a differential LVPECL- or an  
LVCMOS/LVTTL-compatible input clock. The two clock  
sources can be used to provide for a test clock as well as the  
primary system clock. All other control inputs are  
LVCMOS/LVTTL compatible. The eighteen outputs are 2.5V or  
3.3V compatible and can drive two series-terminated 50  
transmission lines. With this capability the B9940L has an  
effective fan-out of 1:36. Low output-to-output skews make the  
B9940L an ideal clock distribution buffer for nested clock trees  
in the most demanding of synchronous systems.  
• LVPECL or LVCMOS/LVTTL clock input  
• LVCMOS/LVTTL compatible inputs  
• 18 clock outputs: drive up to 36 clock lines  
• 150-ps max. output-to-output skew  
• Dual- or single-supply operation:  
— 3.3V core and 3.3V outputs  
— 3.3V core and 2.5V outputs  
— 2.5V core and 2.5V outputs  
• Pin-compatible with MPC940L  
• Industrial temperature range: -40°C to 85°C  
• 32-pin LQFP package  
Block Diagram  
Pin Configuration  
VSS  
VSS  
TCLK  
1
2
3
4
5
6
7
8
24  
23  
22  
21  
Q6  
Q7  
Q8  
VDD  
VDD  
VDDC  
PECL_CLK  
PECL_CLK#  
0
1
TCLK_SEL  
PECL_CLK  
PECL_CLK#  
VDD  
18  
Q0-Q17  
B9940L 20 Q9  
TCLK  
19  
18  
17  
Q10  
Q11  
VSS  
TCLK_SEL  
VDDC  
Cypress Semiconductor Corporation  
Document #: 38-07105 Rev. *C  
3901 North First Street  
San Jose, CA 95134  
408-943-2600  
Revised December 26, 2002  

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