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B9846AYT

更新时间: 2024-01-16 14:59:40
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
7页 60K
描述
Low Skew Clock Driver, 6 True Output(s), 6 Inverted Output(s), PDSO28, SSOP-28

B9846AYT 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:SSOP
包装说明:SSOP,针数:28
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.92输入调节:STANDARD
JESD-30 代码:R-PDSO-G28JESD-609代码:e0
长度:10.2 mm逻辑集成电路类型:LOW SKEW CLOCK DRIVER
湿度敏感等级:1功能数量:1
反相输出次数:6端子数量:28
实输出次数:6最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:SSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, SHRINK PITCH峰值回流温度(摄氏度):220
传播延迟(tpd):6 ns认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.15 ns座面最大高度:2 mm
最大供电电压 (Vsup):2.625 V最小供电电压 (Vsup):2.375 V
标称供电电压 (Vsup):2.5 V表面贴装:YES
温度等级:COMMERCIAL端子面层:TIN LEAD
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:5.3 mm最小 fmax:170 MHz
Base Number Matches:1

B9846AYT 数据手册

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B9846  
2-DIMM DDR Clock Distribution Buffer/Driver  
Features  
Description  
• Supports 266 MHz DDR SDRAM  
• Supports VIA Pro 266, PM266, and KT266 chipsets  
• Operating frequency: 60 MHz – 170 MHz  
• 6 differential pairs  
• Spread-spectrum-compatible  
• Low jitter (cycle-to-cycle): < 75 ps  
• Very low skew: < 100 ps  
• Fast propagation delay: < 4.5nS  
• 50% duty cycle  
• Power management via I2C interface  
• 2.5V power supply  
The B9846 is a high performance, low-skew, low jitter buffer  
designed to distribute differential clocks in high-speed applica-  
tions. The B9846 generates six differential pair clock outputs  
to support two DDR Dimms. In addition, the B9846 features a  
feedback clock output, FBOUT. This output is for the chipset  
or other B9846 devices and/or one of Cypresss zero-delay  
buffers. Typically, The B9846 is used with C9846 clock synthe-  
sizer for the VIA Pro 266 chipset, and with the C9854 clock  
synthesizer for the VIA KT266 chipset.  
The I2C interface enables/disables differential pair outputs.  
This feature allows flexibility in system power management.  
• 28-pin SSOP  
Pin Configuration  
Block Diagram  
FBOUT  
FBOUT  
VSS  
1
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
VSS  
BUFIN  
DDRT0  
DDRC0  
2
DDRT5  
DDRC5  
VDD2.5V  
VSS  
DDRT0  
DDRC0  
VDD2.5V  
VSS  
3
DDRT1  
DDRC1  
4
5
SCLK  
Control  
Logic  
DDRT2  
DDRC2  
6
DDRT4  
DDRC4  
VDD2.5V  
VSS  
DDRT1  
DDRC1  
VDD2.5V  
BUFIN  
VSS  
7
SDATA  
DDRT3  
DDRC3  
8
9
DDRT4  
DDRC4  
10  
11  
12  
13  
14  
DDRT3  
DDRC3  
VDD2.5V  
SCLK  
DDRT5  
DDRC5  
DDRT2  
DDRC2  
VDD2.5V  
SDATA  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
Document #: 38-07299 Rev. *A  
Revised December 22, 2002  

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