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7C4282V/92V-25 PDF预览

7C4282V/92V-25

更新时间: 2022-04-23 23:00:11
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 先进先出芯片
页数 文件大小 规格书
15页 240K
描述
64K/128Kx9 Low Voltage Deep Sync FIFOs w/ Retransmit & Depth Expansion

7C4282V/92V-25 数据手册

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CY7C4282V  
CY7C4292V  
64K/128Kx9 Low Voltage Deep Sync FIFOs  
w/ Retransmit & Depth Expansion  
Features  
Functional Description  
• 3.3V operation for low power consumption and easy  
integration into low-voltage systems  
• High-speed, low-power, first-in first-out (FIFO)  
memories  
• 64K x 9 (CY7C4282V)  
• 128K x 9 (CY7C4292V)  
The CY7C4282V/92V are high-speed, low-power, first-in first-  
out (FIFO) memories with clocked read and write interfaces.  
All devices are 9 bits wide. The CY7C4282V/92V can be cas-  
caded to increase FIFO depth. Programmable features include  
Almost Full/Almost Empty flags. These FIFOs provide solutions  
for a wide variety of data buffering needs, including high-speed data  
acquisition, multiprocessor interfaces, video and communications  
buffering.  
• 0.35 micron CMOS for optimum speed/power  
• High-speed, Near Zero Latency (True Dual-Ported  
Memory Cell), 100-MHz operation (10 ns read/write  
cycle times)  
These FIFOs have 9-bit input and output ports that are con-  
trolled by separate clock and enable signals. The input port is  
controlled by a free-running clock (WCLK) and a Write Enable  
pin (WEN).  
• Low power  
I
I
= 25 mA  
= 6 mA  
CC  
Retransmit and Synchronous Almost Full/Almost Empty flag  
features are available on these devices.  
SB  
• Fully asynchronous and simultaneous read and write  
operation  
• Empty, Full, and Programmable Almost Empty and Al-  
most Full status flags  
Depth expansion is possible using the Cascade Input (XI), Cas-  
cade Output (XO), and First Load (FL) pins. The XO pin is connected  
to the XI pin of the next device, and the XO pin of the last device  
should be connected to the XI pin of the first device. The FL pin of the  
• Retransmit function  
first device is tied to V and the FL pin of all the remaining devices  
SS  
Output Enable (OE pin  
)
should be tied to V  
CC  
• Independent read and write enable pins  
• Supports free-running 50% duty cycle clock inputs  
• Width Expansion Capability  
• Depth Expansion Capability through token-passing  
scheme (no external logic required)  
• 64-pin 10x10 STQFP  
• Pin-compatible 3.3V solution for CY7C4282/92  
When WEN is asserted, data is written into the FIFO on the  
rising edge of the WCLK signal. While WEN is held active, data  
is continually written into the FIFO on each cycle. The output  
port is controlled in a similar manner by a free-running Read  
Clock (RCLK) and a Read Enable pin (REN). In addition, the  
CY7C4282V/92V have an Output Enable pin (OE). The read  
and write clocks may be tied together for single-clock operation  
or the two clocks may be run independently for asynchronous  
read/write applications. Clock frequencies up to 67 MHz are  
achievable.  
D
0 −  
8
Logic  
Diagram  
Block  
INPUT  
REGISTER  
WCLK WEN  
FLAG  
PROGRAM  
REGISTER  
WRITE  
CONTROL  
FF  
FLAG  
EF  
LOGIC  
PAE  
Dual Port  
RAM Array  
PAF/XO  
64K x 9  
WRITE  
POINTER  
128K x 9  
READ  
POINTER  
RESET  
LOGIC  
RS  
THREE-STATE  
OUTPUT REGISTER  
FL/RT  
XI/LD  
READ  
CONTROL  
EXPANSION  
LOGIC  
PAF/XO  
OE  
Q
0 −  
8
RCLK REN  
4282V–1  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
October 18, 1999  

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