fax id: 6139
CY7C374i
UltraLogic™ 128-Macrocell Flash CPLD
Features
Functional Description
• 128 macrocells in eight logic blocks
• 64 I/O pins
• 5 dedicated inputs including 4 clock pins
• In-System Reprogrammable (ISR™) Flash technology
— JTAG interface
The CY7C374i is an In-System Reprogrammable Complex
Programmable Logic Device (CPLD) and is part of the
FLASH370i™ family of high-density, high-speed CPLDs. Like
all members of the FLASH370i family, the CY7C374i is de-
signed to bring the ease of use as well as PCI Local Bus Spec-
ification support and high performance of the 22V10 to
high-density CPLDs.
• Bus Hold capabilities on all I/Os and dedicated inputs
• No hidden delays
• High speed
Like all of the UltraLogic™ FLASH370i devices, the CY7C374i
is electrically erasable and In-System Reprogrammable (ISR),
which simplifies both design and manufacturing flows thereby
reducing costs. The Cypress ISR function is implemented
through a JTAG serial interface. Data is shifted in and out
through the SDI and SDO pin. The ISR interface is enabled
— f
= 125 MHz
MAX
— t = 10 ns
PD
— t = 5.5 ns
S
using the programming voltage pin (ISR ). Additionally, be-
EN
— t
= 6.5 ns
CO
cause of the superior routability of the FLASH370i devices, ISR
often allows users to change existing logic designs while si-
multaneously fixing pinout assignments.
• Fully PCI compliant
• 3.3V or 5.0V I/O operation
• Available in 84-pin PLCC, 84-pin CLCC, and 100-pin
TQFP packages
• Pin compatible with the CY7C373i
The 128 macrocells in the CY7C374i are divided between
eight logic blocks. Each logic block includes 16 macrocells, a
72 x 86 product term array, and an intelligent product term
allocator.
CLOCK
INPUTS
Logic Block Diagram
INPUTS
1
4
INPUT/CLOCK
MACROCELLS
INPUT
MACROCELL
4
4
8 I/Os
LOGIC
BLOCK
A
LOGIC
BLOCK
H
8 I/Os
I/O0–I/O7
36
16
36
16
I/O56–I/O63
PIM
LOGIC
BLOCK
B
LOGIC
BLOCK
G
8 I/Os
8 I/Os
8 I/Os
8 I/Os
36
16
36
16
I/O8–I/O15
I/O16–I/O23
I/O48–I/O55
I/O40–I/O47
LOGIC
BLOCK
C
LOGIC
BLOCK
F
36
16
36
16
8 I/Os
LOGIC
BLOCK
D
LOGIC
BLOCK
E
8 I/Os
36
16
36
16
I/O24–I/O31
I/O32–I/O39
7C374i-1
32
32
Selection Guide
7C374i–125 7C374i–100 7C374i–83
7C374i–66 7C374iL–66
[1]
Maximum Propagation Delay , t (ns)
10
5.5
6.5
125
12
6
15
8
20
10
20
10
10
75
PD
Minimum Set-Up, t (ns)
S
[1]
Maximum Clock to Output , t
(ns)
7
8
10
CO
Typical Supply Current, I (mA)
125
125
125
CC
Note:
1. The 3.3V I/O mode timing adder, t3.3IO, must be added to this specification when VCCIO = 3.3V.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
October 1995 – Revised December 19, 1997