Datasheet > 7C372I-100

7C372I-100

更新时间： 2022-05-11 09:19:49

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
13页	165K
描述
UltraLogic 64-Macrocell Flash CPLD

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7C372I-100 数据手册

CY7C372i

UltraLogic™ 64-Macrocell Flash CPLD

Features

Functional Description

• 64 macrocells in four logic blocks

• 32 I/O pins

The CY7C372i is an In-System Reprogrammable Complex

Programmable Logic Device (CPLD) and is part of the

FLASH370i™ family of high-density, high-speed CPLDs. Like

all members of the FLASH370i family, the CY7C372i is

designed to bring the ease of use and high performance of the

22V10, as well as PCI Local Bus Specification support, to

high-density CPLDs.

• Five dedicated inputs including two clock pins

• In-System Reprogrammable (ISR™) Flash technology

— JTAG interface

• Bus Hold capabilities on all I/Os and dedicated inputs

• No hidden delays

Like all of the UltraLogic™ FLASH370i devices, the CY7C372i

is electrically erasable and ISR, which simplifies both design

and manufacturing flows, thereby reducing costs. The

Cypress ISR function is implemented through a JTAG serial

interface. Data is shifted in and out through the SDI and SDO

pins. The ISR interface is enabled using the programming

voltage pin (ISR_EN). Additionally, because of the superior

routability of the FLASH370i devices, ISR often allows users to

change existing logic designs while simultaneously fixing

pinout assignments.

• High speed

— f_MAX= 125 MHz

— t_PD= 10 ns

— t_S= 5.5 ns

— t_CO= 6.5 ns

• Fully PCI compliant

The 64 macrocells in the CY7C372i are divided between four

logic blocks. Each logic block includes 16 macrocells, a

72 x 86 product term array, and an intelligent product term

allocator.

• 3.3V or 5.0V I/O operation

• Available in 44-pin PLCC, TQFP, and CLCC packages

• Pin-compatible with the CY7C371i

The logic blocks in the FLASH370i architecture are connected

with an extremely fast and predictable routing resource—the

Programmable Interconnect Matrix (PIM). The PIM brings

flexibility, routability, speed, and a uniform delay to the inter-

connect.

Logic Block Diagram

CLOCK

INPUTS

INPUT/CLOCK

MACROCELLS

INPUT

MACROCELLS

8 I/Os

LOGIC

BLOCK

LOGIC

BLOCK

I/O₀-I/O₇

I/O₂₄-I/O₃₁

PIM

LOGIC

BLOCK

LOGIC

BLOCK

I/O₈-I/O₁₅

I/O₁₆-I/O₂₃

Cypress Semiconductor Corporation

Document #: 38-03033 Rev. *A

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Revised April 16, 2004

12 3 4 5 6 7...13

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