Datasheet > 7C1019BV33-10

7C1019BV33-10

更新时间： 2022-11-24 21:53:46

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
7页	241K
描述
128K x 8 Static RAM

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数据手册

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7C1019BV33-10 数据手册

CY7C1019BV33

128K x 8 Static RAM

Writing to the device is accomplished by taking Chip Enable

(CE) and Write Enable (WE) inputs LOW. Data on the eight I/O

Features

• High speed

pins (I/O through I/O ) is then written into the location speci-

fied on the address pins (A through A ).

— t = 10 ns

Reading from the device is accomplished by taking Chip

Enable (CE) and Output Enable (OE) LOW while forcing Write

Enable (WE) HIGH. Under these conditions, the contents of

the memory location specified by the address pins will appear

on the I/O pins.

• CMOS for optimum speed/power

• Center power/ground pinout

• Automatic power-down when deselected

• Easy memory expansion with CE and OE options

• Functionally equivalent to CY7C1019V33

The eight input/output pins (I/O through I/O ) are placed in a

high-impedance state when the device is deselected (CE

HIGH), the outputs are disabled (OE HIGH), or during a write

operation (CE LOW, and WE LOW).

Functional Description

The CY7C1019BV33 is a high-performance CMOS static

RAM organized as 131,072 words by 8 bits. Easy memory

expansion is provided by an active LOW Chip Enable (CE), an

active LOW Output Enable (OE), and three-state drivers. This

device has an automatic power-down feature that significantly

reduces power consumption when deselected.

The CY7C1019BV33 is available in a standard 400-mil-wide

package.

Logic Block Diagram

Pin Configurations

SOJ

Top View

I/O

INPUT BUFFER

I/O

512 x 256 x 8

ARRAY

I/O

POWER

DOWN

COLUMN

DECODER

I/O

1019BV33–2

1019BV33–1

Selection Guide

7C1019BV33-10

7C1019BV33-12

7C1019BV33-15

Maximum Access Time (ns)

175

160

145

Maximum Operating Current (mA)

Maximum Standby Current (mA)

−

0.5

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

January 19, 2001

12 3 4 5 6 7

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