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5962-9951901QYA PDF预览

5962-9951901QYA

更新时间: 2024-01-03 12:48:32
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 可编程逻辑器件输入元件时钟
页数 文件大小 规格书
64页 1733K
描述
5V, 3.3V, ISRTM High-Performance CPLDs

5962-9951901QYA 技术参数

生命周期:Active零件包装代码:LCC
包装说明:QCCJ,针数:44
Reach Compliance Code:compliantECCN代码:3A001.A.2.C
HTS代码:8542.39.00.01风险等级:5.77
Is Samacsys:N最大时钟频率:83 MHz
JESD-30 代码:S-CQCC-J44JESD-609代码:e0
长度:16.4846 mm专用输入次数:1
I/O 线路数量:37端子数量:44
最高工作温度:125 °C最低工作温度:-55 °C
组织:1 DEDICATED INPUTS, 37 I/O输出函数:MACROCELL
封装主体材料:CERAMIC, METAL-SEALED COFIRED封装代码:QCCJ
封装形状:SQUARE封装形式:CHIP CARRIER
可编程逻辑类型:EE PLD传播延迟:10 ns
认证状态:Qualified筛选级别:MIL-PRF-38535 Class Q
座面最大高度:4.826 mm最大供电电压:5.5 V
最小供电电压:4.5 V标称供电电压:5 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:TIN LEAD
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD宽度:16.4846 mm
Base Number Matches:1

5962-9951901QYA 数据手册

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Ultra37000 CPLD Family  
5V, 3.3V, ISR™ High-Performance CPLDs  
Features  
General Description  
• In-System Reprogrammable™ (ISR™) CMOS CPLDs  
— JTAG interface for reconfigurability  
— Design changes do not cause pinout changes  
— Design changes do not cause timing changes  
• High density  
The Ultra37000™ family of CMOS CPLDs provides a range of  
high-density programmable logic solutions with unparalleled  
system performance. The Ultra37000 family is designed to  
bring the flexibility, ease of use, and performance of the 22V10  
to high-density CPLDs. The architecture is based on a number  
of logic blocks that are connected by a Programmable Inter-  
connect Matrix (PIM). Each logic block features its own  
product term array, product term allocator, and 16 macrocells.  
The PIM distributes signals from the logic block outputs and all  
input pins to the logic block inputs.  
— 32 to 512 macrocells  
— 32 to 264 I/O pins  
— Five dedicated inputs including four clock pins  
• Simple timing model  
All of the Ultra37000 devices are electrically erasable and  
In-System Reprogrammable (ISR), which simplifies both  
design and manufacturing flows, thereby reducing costs. The  
ISR feature provides the ability to reconfigure the devices  
without having design changes cause pinout or timing  
changes. The Cypress ISR function is implemented through a  
JTAG-compliant serial interface. Data is shifted in and out  
through the TDI and TDO pins, respectively. Because of the  
superior routability and simple timing model of the Ultra37000  
devices, ISR allows users to change existing logic designs  
while simultaneously fixing pinout assignments and  
maintaining system performance.  
— No fanout delays  
— No expander delays  
— No dedicated vs. I/O pin delays  
— No additional delay through PIM  
— No penalty for using full 16 product terms  
— No delay for steering or sharing product terms  
• 3.3V and 5V versions  
• PCI-compatible[1]  
The entire family features JTAG for ISR and boundary scan,  
and is compatible with the PCI Local Bus specification,  
meeting the electrical and timing requirements. The  
Ultra37000 family features user programmable bus-hold  
capabilities on all I/Os.  
• Programmable bus-hold capabilities on all I/Os  
• Intelligent product term allocator provides:  
— 0 to 16 product terms to any macrocell  
— Product term steering on an individual basis  
— Product term sharing among local macrocells  
• Flexible clocking  
Ultra37000 5.0V Devices  
The Ultra37000 devices operate with a 5V supply and can  
support 5V or 3.3V I/O levels. VCCO connections provide the  
capability of interfacing to either a 5V or 3.3V bus. By  
connecting the VCCO pins to 5V the user insures 5V TTL levels  
on the outputs. If VCCO is connected to 3.3V the output levels  
meet 3.3V JEDEC standard CMOS levels and are 5V tolerant.  
These devices require 5V ISR programming.  
— Four synchronous clocks per device  
— Product term clocking  
— Clock polarity control per logic block  
• Consistent package/pinout offeringacrossall densities  
— Simplifies design migration  
Ultra37000V 3.3V Devices  
— Same pinout for 3.3V and 5.0V devices  
• Packages  
Devices operating with a 3.3V supply require 3.3V on all VCCO  
pins, reducing the device’s power consumption. These  
devices support 3.3V JEDEC standard CMOS output levels,  
and are 5V-tolerant. These devices allow 3.3V ISR  
programming.  
— 44 to 400 leads in PLCC, CLCC, PQFP, TQFP, CQFP,  
BGA, and Fine-Pitch BGA packages  
— Lead(Pb)-free packages available  
Note:  
1. Due to the 5V-tolerant nature of 3.3V device I/Os, the I/Os are not clamped to V , PCI V = 2V.  
CC  
IH  
Cypress Semiconductor Corporation  
Document #: 38-03007 Rev. *D  
3901 North First Street  
San Jose, CA 95134  
408-943-2600  
Revised October 25, 2004  

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