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5962-9736101QYAX PDF预览

5962-9736101QYAX

更新时间： 2024-02-05 02:44:39
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 存储先进先出芯片
页数 文件大小 规格书
18页 548K
描述
FIFO, 32KX9, 10ns, Synchronous, CMOS, CQCC32, CERAMIC, LCC-32

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5962-9736101QYAX 技术参数

生命周期：Obsolete零件包装代码：QFJ
包装说明：QCCN,针数：32
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.32.00.71风险等级：5.84
最长访问时间：10 ns其他特性：RETRANSMIT
周期时间：15 ns长度：13.97 mm
内存密度：294912 bit内存宽度：9
功能数量：1字数：32768 words
字数代码：32000工作模式：SYNCHRONOUS
最高工作温度：125 °C最低工作温度：-55 °C
组织：32KX9可输出：YES
封装主体材料：CERAMIC, METAL-SEALED COFIRED封装代码：QCCN
封装形式：CHIP CARRIER并行/串行：PARALLEL
认证状态：Not Qualified筛选级别：MIL-PRF-38535 Class Q
座面最大高度：2.286 mm最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：MILITARY端子形式：NO LEAD
端子节距：1.27 mm端子位置：QUAD
宽度：11.43 mmBase Number Matches：1

5962-9736101QYAX 数据手册

 浏览型号5962-9736101QYAX的Datasheet PDF文件第2页浏览型号5962-9736101QYAX的Datasheet PDF文件第3页浏览型号5962-9736101QYAX的Datasheet PDF文件第4页浏览型号5962-9736101QYAX的Datasheet PDF文件第5页浏览型号5962-9736101QYAX的Datasheet PDF文件第6页浏览型号5962-9736101QYAX的Datasheet PDF文件第7页 
16K/32K  
x 9 Deep Sync FIFOsCY7C4271CY7C4261  
CY7C4261  
CY7C4271  
16K/32K x 9 Deep Sync FIFOs  
• Pb-Free Packages Available  
Features  
Functional Description  
• High-speed, low-power, first-in first-out (FIFO)  
memories  
The CY7C4261/71 are high-speed, low-power FIFO  
memories with clocked read and write interfaces. All are nine  
bits wide. The CY7C4261/71 are pin-compatible to the  
CY7C42X1 Synchronous FIFO family. The CY7C4261/71 can  
be cascaded to increase FIFO width. Programmable features  
include Almost Full/Almost Empty flags. These FIFOs provide  
solutions for a wide variety of data buffering needs, including  
high-speed data acquisition, multiprocessor interfaces, and  
communications buffering.  
• 16K × 9 (CY7C4261)  
• 32K × 9 (CY7C4271)  
• 0.5-micron CMOS for optimum speed/power  
• High-speed 100-MHz operation (10-ns read/write cycle  
times)  
• Low power — ICC = 35 mA  
• Fully asynchronous and simultaneous read and write  
operation  
These FIFOs have 9-bit input and output ports that are  
controlled by separate clock and enable signals. The input port  
is controlled by a free-running clock (WCLK) and two  
write-enable pins (WEN1, WEN2/LD).  
• Empty, Full, HalfFull, andprogrammableAlmostEmpty  
and Almost Full status flags  
• TTL-compatible  
When WEN1 is LOW and WEN2/LD is HIGH, data is written  
into the FIFO on the rising edge of the WCLK signal. While  
WEN1, WEN2/LD is held active, data is continually written into  
the FIFO on each WCLK cycle. The output port is controlled in  
a similar manner by a free-running read clock (RCLK) and two  
read enable pins (REN1, REN2). In addition, the CY7C4261/71  
has an output enable pin (OE). The read (RCLK) and write  
(WCLK) clocks may be tied together for single-clock operation  
or the two clocks may be run independently for asynchronous  
read/write applications. Clock frequencies up to 100 MHz are  
achievable. Depth expansion is possible using one enable  
input for system control, while the other enable is controlled by  
expansion logic to direct the flow of data.  
• Output Enable (OE) pins  
• Independent read and write enable pins  
• Center power and ground pins for reduced noise  
• Supports free-running 50% duty cycle clock inputs  
• Width-Expansion Capability  
• Military temp SMD Offering – CY7C4271-15LMB  
• 32-pin PLCC/LCC and 32-pin TQFP  
• Pin-compatible density upgrade to CY7C42X1 family  
• Pin-compatible density upgrade to  
IDT72201/11/21/31/41/51  
PLCC/LCC  
Top View  
D
Logic Block Diagram  
0–8  
Pin Configuration  
INPUT  
REGISTER  
4
3
2
1
32 31 30  
29  
D
RS  
1
5
6
7
D
28  
27  
26  
0
WEN1  
WCLK  
WEN2/LD  
PAF  
PAE  
WCLK WEN1 WEN2/LD  
8
9
CY7C4261  
CY7C4271  
GND  
FLAG  
PROGRAM  
REGISTER  
V
CC  
25  
24  
23  
22  
21  
REN1  
RCLK  
REN2  
OE  
Q
8
10  
11  
12  
13  
Q
7
Q
6
Q
5
WRITE  
CONTROL  
EF  
14 15 16 17 18 19 20  
PAE  
PAF  
FF  
FLAG  
LOGIC  
TQFP  
RAM  
Top View  
ARRAY  
16Kx 9  
32Kx 9  
WRITE  
POINTER  
READ  
POINTER  
32 31 30 29 28 27 26 25  
1
2
3
4
5
6
7
8
24  
WEN1  
D
1
D
0
RESET  
LOGIC  
23  
WCLK  
RS  
WEN2/LD  
22  
21  
20  
19  
PAF  
PAE  
CY7C4261  
CY7C4271  
V
CC  
THREE-STATE  
OUTPUT REGISTER  
Q
8
GND  
REN1  
READ  
CONTROL  
Q
7
Q
6
RCLK  
REN2  
18  
17  
OE  
Q
5
Q
9
10 11 12 13 14 15 16  
0–8  
RCLK REN1 REN2  
Cypress Semiconductor Corporation  
Document #: 38-06015 Rev. *C  
•
3901 North First Street  
•
San Jose, CA 95134  
•
408-943-2600  
Revised August 2, 2005  
1234567...18

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