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5962-01-418-4492 PDF预览

5962-01-418-4492

更新时间: 2024-01-22 13:12:37
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 可编程只读存储器OTP只读存储器电动程控只读存储器电可擦编程只读存储器内存集成电路
页数 文件大小 规格书
13页 378K
描述
EEPROM Card, 8KX8, 25ns, CMOS, CQCC28,

5962-01-418-4492 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:ObsoleteReach Compliance Code:compliant
风险等级:5.8最长访问时间:25 ns
I/O 类型:COMMONJESD-30 代码:S-XQCC-N28
JESD-609代码:e0内存密度:65536 bit
内存集成电路类型:EEPROM CARD内存宽度:8
湿度敏感等级:1端子数量:28
字数:8192 words字数代码:8000
最高工作温度:125 °C最低工作温度:-55 °C
组织:8KX8输出特性:REGISTERED
封装主体材料:CERAMIC封装代码:QCCN
封装等效代码:LCC28,.45SQ封装形状:SQUARE
封装形式:CHIP CARRIER峰值回流温度(摄氏度):225
电源:5 V编程电压:2.7 V
认证状态:Not Qualified筛选级别:38535Q/M;38534H;883B
最大待机电流:0.12 A子类别:OTP ROMs
最大压摆率:0.12 mA标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:TIN LEAD
端子形式:NO LEAD端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
Base Number Matches:1

5962-01-418-4492 数据手册

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65  
CY7C265  
8K x 8 Registered PROM  
are enabled. One pin on the CY7C265 is programmed to per-  
form either the enable or the initialize function.  
Features  
• CMOS for optimum speed/power  
• High speed (commercial and military)  
— 15 ns address set-up  
If the asynchronous enable (E) is being used, the outputs may  
be disabled at any time by switching the enable to a logic  
HIGH, and may be returned to the active state by switching the  
enable to a logic LOW.  
— 12 ns clock to output  
• Low power  
If the synchronous enable (ES) is being used, the outputs will  
go to the OFF or high-impedance state upon the next positive  
clock edge after the synchronous enable input is switched to a  
HIGH level. If the synchronous enable pin is switched to a logic  
LOW, the subsequent positive clock edge will return the output  
tothe activestate. Followingapositive clock edge, theaddress  
and synchronous enable inputs are free to change since no  
change in the output will occur until the next LOW-to-HIGH  
transitionof theclock. This uniquefeatureallows the CY7C265  
decoders and sense amplifiers to access the next location  
whilepreviously addresseddataremains stable on theoutputs.  
— 660 mW (commercial)  
— 770 mW (military)  
• On-chip edge-triggered registers  
— Ideal for pipelined microprogrammed systems  
• EPROM technology  
— 100% programmable  
— Reprogrammable (7C265W)  
• 5V ±10% VCC, commercial and military  
• Capable of withstanding >2001V static discharge  
• Slim 28-pin, 300-mil plastic or hermetic DIP  
If the E/I pin is used for INIT (asynchronous), then the outputs  
are permanently enabled. The initialize function is useful dur-  
ing power-up and time-out sequences, and can facilitate im-  
plementation of other sophisticated functions such as a built-in  
jump startaddress. When activated, the initialize control in-  
put causes the contents of a user programmed 8193rd 8-bit  
word to be loaded into the on-chip register. Each bit is pro-  
grammable and the initialize function can be used to load any  
desired combination of 1s and 0s into the register. In the un-  
programmed state, activating INIT will generate a register  
clear (all outputs LOW). If all the bits of the initialize word are  
programmed to be a 1, activating INIT performs a register pre-  
set (all outputs HIGH).  
Functional Description  
The CY7C265 is a 8192 x 8 registered PROM. It is organized  
as 8,192 words by 8 bits wide, and has a pipeline output reg-  
ister. In addition, the device features a programmable initialize  
byte that may be loaded into the pipeline register with the ini-  
tialize signal. The programmable initialize byte is the 8,193rd  
byte in the PROM and its value is programmed at the time of  
use.  
Packaged in 28 pins, the PROM has 13 address signals (A0  
through A12), 8 data out signals (O0 through O7), E/I (enable  
or initialize), and CLOCK.  
Applying a LOW to the INIT input causes an immediate load of  
the programmed initialize word into the pipeline register and  
onto the outputs. The INIT LOW disables clock and must return  
HIGH to enable clock independent of all other inputs, including  
the clock.  
CLOCK functions as a pipeline clock, loading the contents of  
the addressed memory location into the pipeline register on  
each rising edge. The data will appear on the outputs if they  
Cypress Semiconductor Corporation  
Document #: 38-04012 Rev. **  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
Revised March 14, 2002  

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