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39K165 PDF预览

39K165

更新时间: 2022-11-24 21:47:48
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
86页 1209K
描述
CPLDs at FPGA DensitiesTM

39K165 数据手册

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Delta39K™ ISR™  
CPLD Family  
CPLDs at FPGA Densities™  
• Carry-chain logic for fast and efficient arithmetic opera-  
tions  
Features  
• High density  
• Multiple I/O standards supported  
— 30K to 200K usable gates  
— 512 to 3072 macrocells  
— 136 to 428 maximum I/O pins  
LVCMOS (3.3/3.0/2.5/1.8V), LVTTL, 3.3V PCI, SSTL2  
(I-II), SSTL3 (I-II), HSTL (I-IV), and GTL+  
• Compatible with NOBL™, ZBT™, and QDR™ SRAMs  
• Programmable slew rate control on each I/O pin  
• User-programmableBusHoldcapabilityoneachI/O pin  
• Fully 3.3V PCI-compliant (to 66-MHz 64-bit PCI spec,  
rev. 2.2)  
— Twelve dedicated inputs including four clock pins,  
four global I/O control signal pins and four JTAG  
interface pins for boundary scan and reconfig-  
urability  
• CompactPCI hot swap ready  
• Embedded memory  
• Multiple package/pinout offering across all densities  
208 to 676 pins in PQFP, BGA, and FBGA packages  
Simplifies design migration across density  
Self-Boot™ solution in BGA and FBGA packages  
• In-System Reprogrammable™ (ISR™)  
— 80K to 480K bits embedded SRAM  
• 16K to 96K bits of (dual-port) channel memory  
• High speed – 233-MHz in-system operation  
• AnyVolt™ interface  
— 3.3V, 2.5V,1.8V, and 1.5V I/O capability  
• Low-power operation  
JTAG-compliant on-board programming  
— 0.18-mm six-layer metal SRAM-based logic process  
Design changes do not cause pinout changes  
• IEEE1149.1 JTAG boundary scan  
— Full-CMOS implementation of product term array  
— Standby current as low as 5mA  
• Simple timing model  
Development Software  
— No penalty for using full 16 product terms/macrocell  
— No delay for single product term steering or sharing  
• Flexible clocking  
— Spread Aware™ PLL drives all four clock networks  
• Allows 0.6% spread spectrum input clocks  
• Several multiply, divide and phase shift options  
— Four synchronous clock networks per device  
— Locally generated product term clock  
— Clock polarity control at each register  
Warp®  
IEEE 1076/1164 VHDL or IEEE 1364 Verilog context  
sensitive editing  
— Active-HDL FSM graphical finite state machine editor  
Active-HDL SIM post-synthesis timing simulator  
Architecture Explorer for detailed design analysis  
Static Timing Analyzer for critical path analysis  
Available on Windows95/98/2000/XP™ and  
Windows NT™ for $99  
Supports all Cypress programmable logic products  
Delta39K™ ISR CPLD Family Members  
[2]  
Standby ICC  
Cluster Channel  
Speed-tPD  
TA = 25°C  
3.3/2.5V  
5 mA  
Typical  
Gates[1]  
memory memory Maximum fMAX2 Pin-to-Pin  
Device  
39K30  
Macrocells  
512  
(Kbits)  
64  
(Kbits)  
16  
I/O Pins  
174  
(MHz)  
233  
(ns)  
7.2  
7.2  
7.5  
8.5  
8.5  
16K – 48K  
23K – 72K  
46K – 144K  
77K – 241K  
92K – 288K  
39K50  
768  
96  
24  
218  
233  
5 mA  
39K100  
39K165  
39K200  
1536  
192  
320  
384  
48  
302  
222  
10 mA  
20 mA  
20 mA  
2560  
80  
386  
181  
3072  
96  
428  
181  
Notes:  
1. Upper limit of typical gates is calculated by assuming only 10% of the channel memory is used.  
2. Standby ICC values are with PLL not utilized, no output load and stable inputs.  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
Document #: 38-03039 Rev. *H  
Revised August 1, 2003  

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