1CY27H010
fax id: 3023
CY27H010
128K x 8 High-Speed CMOS EPROM
try-standard 32-pin, 600-mil DIP, LCC, PLCC, and TSOP-I
packages. These devices offer high-density storage com-
bined with 40-MHz performance. The CY27H010 is available
in windowed and opaque packages. Windowed packages al-
low the device to be erased with UV light for 100% re-
programmability.
Features
• CMOS for optimum speed/power
• High speed
— t = 25 ns max. (commercial)
AA
— t = 35 ns max. (military)
AA
The CY27H010 is equipped with a power-down chip enable
(CE) input and output enable (OE). When CE is deasserted,
the device powers down to a low-power stand-by mode. The
OE pin three-states the outputs without putting the device into
stand-by mode. While CE offers lower power, OE provides a
more rapid transition to and from three-stated outputs.
• Low power
— 275 mW max.
— Less than 85 mW when deselected
• Byte-wide memory organization
• 100% reprogrammable in thewindowed package
• EPROM technology
• Capable of withstanding >2001V static discharge
• Available in
The memory cells utilize proven EPROM floating-gate technol-
ogy and byte-wide intelligent programming algorithms. The
EPROM cell requires only 12.75 V for the supervoltage and
low programming current allows for gang programming. The
device allows for each memory location to be tested 100%,
because each location is written to, erased, and repeatedly
exercised prior to encapsulation. Each device is also tested
for AC performance to guarantee that the product will meet DC
and AC specification limits after customer programming.
— 32-pin PLCC
— 32-pin TSOP-I
— 32-pin, 600-mil plastic or hermetic DIP
— 32-pin hermetic LCC
The CY27H010 is read by asserting both the CE and the OE
inputs. The contents of the memory location selected by the
Functional Description
address on inputs A –A will appear at the outputs O –O .
16
0
7
0
The CY27H010 is a high-performance, 1-megabit CMOS
EPROM organized in 128 Kbytes. It is available in indus-
Logic Block Diagram
Pin Configurations
DIP
A
0
Top View
O
0
A
1
V
32
31
30
V
1
CC
PP
A
2
A
A
A
PGM
NC
2
3
4
16
15
12
O
1
O
2
O
3
A
3
PROGRAMMABLE
ARRAY
A
14
29
28
A
4
A
5
A
13
7
27
26
A
A
5
6
A
A
6
A
5
8
7
9
A
6
25
24
23
22
21
A
8
9
10
11
12
13
A
11
4
A
3
OE
A
MULTIPLEXER
7
ADDRESS
DECODER
A
2
A
10
O
O
A
8
4
CE
O
O
6
A
1
A
7
0
0
1
A
9
O
O
O
20
19
5
6
7
O
5
A
10
11
12
13
14
15
16
O
4
O
3
2
18
17
A
A
A
GND
O
O
POWER DOWN
H010–2
LCC/PLCC
Top View
A
A
14
15
16
4
3
2
323130
1
A
A
A
A
A
A
A
29
14
7
5
6
7
8
A
6
28
27
26
25
24
23
22
21
13
8
A
5
A
4
9
A
11
3
9
CE
OE
A
OE
2
10
11
12
13
OUTPUT ENABLE
DECODER
A
A
10
1
A
CE
O
0
O
0
7
14151617 181920
H010–1
H010–3
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
August 1994 – Revised March 1997
5秒后页面跳转
MAX487芯片引脚图及功能、应用领域详解
IR2110驱动芯片引脚图及功能、电路图详解
74LS74是什么芯片 74LS74引脚图及功能表
CD4511芯片引脚图及功能、电路图解析
微信公众号
抖音公众号
浙公网安备 33010502006866号 浙ICP备10014259号-119
营业执照ICP证
数据手册
如果您发现信息不准确，
