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FX802LS PDF预览

FX802LS

更新时间: 2024-02-15 15:26:16
品牌 Logo 应用领域
CMLMICRO /
页数 文件大小 规格书
14页 129K
描述
DVSR CODEC

FX802LS 技术参数

生命周期:Transferred包装说明:SMALL OUTLINE, R-PDSO-F6
Reach Compliance Code:unknownECCN代码:EAR99
风险等级:5.54外壳连接:COLLECTOR
最大集电极电流 (IC):5 A集电极-发射极最大电压:20 V
配置:SINGLE WITH BUILT-IN DIODE最小直流电流增益 (hFE):200
JESD-30 代码:R-PDSO-F6元件数量:1
端子数量:6封装主体材料:PLASTIC/EPOXY
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
极性/信道类型:PNP功耗环境最大值:1.5 W
认证状态:Not Qualified表面贴装:YES
端子形式:FLAT端子位置:DUAL
晶体管应用:SWITCHING晶体管元件材料:SILICON
Base Number Matches:1

FX802LS 数据手册

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FX802  
DVSR CODEC  
SERIAL  
CLOCK  
COMMAND  
DATA  
REPLY  
DATA  
XTAL/  
CLOCK  
AUDIO  
IN  
AUDIO  
OUT  
IRQ  
XTAL  
CS  
AUDIO  
BYPASS  
CLOCK  
C-BUS INTERFACE AND CONTROL LOGIC  
GENERATOR  
DECODER  
OUTPUT  
BIAS  
V
STATUS  
CONTROL  
REGISTER  
REGISTER  
STORE  
PLAY  
COMMAND  
BUFFER  
COMMAND  
BUFFER  
ENCODE  
CLOCK  
DECODE  
CLOCK  
DATA  
READ  
DATA  
WRITE  
SPEECH  
STORE  
SPEECH  
PLAY  
POWER  
ASSESS  
MOD  
DEMOD  
COUNTER  
COUNTER  
COUNTERS  
COUNTERS  
ENCODER  
CLOCK  
DECODER  
CLOCK  
IDLE  
PATTERN  
DRAM CONTROL AND TIMING  
DIRECT ACCESS CLOCKS and DATA  
CAS  
RAS 2 RAS 3 RAS 4  
RAS 1  
WE  
VSS  
VDD  
VBIAS  
A9  
A8  
A7  
A6  
A5  
A4  
A3/ECK  
A2/DCK  
A0/ENO  
(ENCODER  
OUT)  
A1/ DEI  
(DECODER  
IN)  
DRAM ADDRESS LINES  
Fig.1 FX802 DVSR Codec  
Brief Description  
The FX802 DVSR Codec contains:  
The FX802 may also be used without DRAM (as a “stand-  
alone” CVSD Codec), in which case direct access is  
provided to the CVSD Codec digital data and clock signals.  
A Continuously Variable Slope Delta Modulation (CVSD)  
encoder and decoder.  
All functions are controlled by “C-BUS” commands from  
the system µController.  
Control and timing circuitry for up to 4Mbits of external  
Dynamic Random Access Memory (DRAM).  
The Storage, Recovery and Replay functions of the  
FX802 can be used for:  
“C-BUS” µProcessor interface and control logic.  
When used with external DRAM, the FX802 has four primary  
functions:  
Answering Machine applications, where an incoming  
speech message is stored for later recall.  
Speech Storage  
Busy Buffering, an outgoing speech message is stored  
Speech signals present at the Audio Input may be digitized  
by the CVSD encoder, and the resulting bit stream stored  
in DRAM. This process also provides readings of input  
power level for use by the system µController.  
temporarily until the transmit channel becomes free.  
Automatic transmission of pre-recorded ‘Alarm’ or  
status announcements.  
Time Domain Scrambling of speech messages.  
VOX control of transmitter functions.  
Speech Playback  
Previously digitized speech data may be read from DRAM  
and converted back into analogue form by the CVSD  
decoder.  
Temporary Data Storage applications, such as  
buffering of over-air data transmissions.  
On-chip the Delta Codec is supported by input and output  
analogue switched-capacitor filters and audio output  
switching circuitry. The DRAM control and timing circuitry  
provides all the necessary address, control and refresh  
signals to interface to external DRAM.  
Data Storage  
Digital data sent over the “C-BUS” from the system  
µController may be stored in DRAM.  
Data Retrieval  
Digital data may be read from DRAM and sent over  
“C-BUS” to the system µController.  
The FX802 DVSR Codec is a low-power 5-volt CMOS LSI  
device.  
Speech storage and playback may be performed  
concurrently with data storage or retrieval.  
Publication D/802/4 December 1995  

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