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FX629 PDF预览

FX629

更新时间: 2024-02-19 18:42:09
品牌 Logo 应用领域
CMLMICRO 解码器编解码器
页数 文件大小 规格书
10页 95K
描述
Delta Modulation Codec

FX629 技术参数

生命周期:Obsolete零件包装代码:DIP
包装说明:DIP,针数:22
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.84Is Samacsys:N
压伸定律:CVSD滤波器:YES
JESD-30 代码:R-GDIP-T22长度:27.175 mm
功能数量:1端子数量:22
工作模式:SYNCHRONOUS/ASYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:CERAMIC, GLASS-SEALED
封装代码:DIP封装形状:RECTANGULAR
封装形式:IN-LINE认证状态:Not Qualified
座面最大高度:5.84 mm标称供电电压:5 V
表面贴装:NO技术:CMOS
电信集成电路类型:CVSD CODEC温度等级:INDUSTRIAL
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL宽度:10.16 mm
Base Number Matches:1

FX629 数据手册

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CML Semiconductor Products  
PRODUCT INFORMATION  
Delta Modulation Codec  
FX629  
Publication D/629/2 July 1994  
Provisional Issue  
Features/Applications  
Designed to Meet Mil-Std-188-113  
Military Communications  
Programmable Sampling Clocks  
3 or 4-bit Compand Algorithm  
Forced Idle Facility  
Delta MUX, Switch and Phone  
Applications  
Powersave Facility  
Single 5V CMOS Process  
Single-Chip Full-Duplex Codec  
On-Chip Input and Output Filters  
Full-Duplex CVSD* Codec  
DATA ENABLE  
ENCODER FORCE IDLE  
ENCODER INPUT  
MOD  
VDD  
VSS  
ENCODER OUTPUT  
f1  
f 2  
XTAL/CLOCK  
f 0  
XTAL  
CLOCK RATE  
ENCODER DATA CLOCK  
DECODER DATA CLOCK  
VBIAS  
GENERATORS  
FX629  
MODE 1  
CLOCK MODE  
LOGIC  
MODE 2  
SAMPLING RATE  
CONTROL  
ALGORITHM  
3 or 4-BIT  
POWERSAVE  
f 3  
f 1  
DECODER INPUT  
DEMOD  
DECODER OUTPUT  
DECODER FORCE IDLE  
Fig.1 Internal Block Diagram  
Brief Description  
The FX629 is an LSI circuit designed as a  
The encoder has an enable function for use in  
*Continuously Variable Slope Delta Codec and multiplexer applications.  
is intended for use in military communications  
systems.  
Designed to meet Mil-Std-188-113 with  
Encoder and Decoder forced idle facilities are  
provided, forcing a 10101010..... pattern in  
encode and a VDD/2 bias in decode.  
external components, the device is suitable for The companding circuits may be operated with  
applications in military Delta Multiplexers,  
switches and phones.  
Encoder input and decoder output filters are  
a pin-selected 3 or 4-bit algorithm.  
The powersave facility puts the device into the  
standby mode thereby reducing current  
incorporated on-chip. Sampling clock rates can consumption when not operating.  
be programmed to 16, 32 or 64 k bits/second  
from an internal clock generator or may be  
externally applied in the range 8 to 64 k bits/  
A reference 1.024MHz oscillator uses an  
external clock pulse or Xtal input.  
The FX629 is a low-power, 5 volt CMOS  
second. Sampling clock frequencies are output device and is available in 22-pin cerdip DIL  
for the synchronization of external circuits. package.  

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