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CS7054YN14 PDF预览

CS7054YN14

更新时间: 2024-02-05 03:16:54
品牌 Logo 应用领域
樱桃 - CHERRY 驱动器MOSFET驱动器驱动程序和接口接口集成电路光电二极管控制器
页数 文件大小 规格书
6页 147K
描述
Low Side PWM FET Controller

CS7054YN14 技术参数

生命周期:Active零件包装代码:DIP
包装说明:DIP,针数:14
Reach Compliance Code:unknown风险等级:5.75
高边驱动器:YES接口集成电路类型:BUFFER OR INVERTER BASED MOSFET DRIVER
JESD-30 代码:R-PDIP-T14长度:18.86 mm
功能数量:1端子数量:14
最高工作温度:125 °C最低工作温度:-40 °C
标称输出峰值电流:0.4 A封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装形状:RECTANGULAR
封装形式:IN-LINE认证状态:COMMERCIAL
座面最大高度:4.69 mm最大供电电压:16 V
最小供电电压:8 V标称供电电压:12 V
表面贴装:NO温度等级:AUTOMOTIVE
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL宽度:7.62 mm
Base Number Matches:1

CS7054YN14 数据手册

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CS7054  
Low Side PWM FET Controller  
Features  
Description  
The CS7054 is a monolithic integrat- potentiometer referenced to the on-  
200 mA Peak PWM Gate  
ed circuit designed primarily to  
control the rotor speed of perma-  
nent magnet, direct current (DC)  
brush motors. It drives the gate of  
an N channel power MOSFET or  
IGBT with a user-adjustable, fixed  
frequency, variable duty cycle,  
pulse width modulated (PWM) sig-  
nal. The CS7054 can also be used to  
control other loads such as incan-  
descent bulbs and solenoids.  
chip 5V linear regulator, or a fil-  
tered 0% to 100% PWM signal also  
referenced to the 5V regulator.  
Drive Output  
Patented Voltage  
The IC is placed in a sleep state by  
pulling the CTL lead below 0.5V. In  
this mode everything on the chip is  
shut down except for the on-chip  
regulator and the overall current  
draw is less than 275 µA. There are  
a number of on-chip diagnostics  
that look for potential failure modes  
and can disable the external power  
MOSFET.  
Compensation Circuit  
100% Duty Cycle  
Capability  
5V, ± 3% Linear Reg.  
Low Current Sleep Mode  
Overvoltage Protection  
Inductive current from the motor or  
solenoid is recirculated through an  
external diode.  
Over Current Protection  
of External MOSFET /  
IGBT  
The CS7054 accepts a DC level  
input signal of 0 to 5V to control the  
pulse width of the output signal.  
This signal can be generated by a  
Output Inhibit  
Application Diagram  
Package Options  
MOT+  
14 Lead PDIP  
RGATE  
6
VBAT  
RS  
51  
42.5mH  
MOT-  
.01mF  
10mF  
OUTPUT  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
1000mF  
VCC  
1000mF  
1M  
Gnd  
FLT  
PGnd  
INH  
OUTPUT  
VCC  
PGnd  
INH  
Gnd  
FLT  
.25mF  
CFLT  
COSC  
COSC  
ROSC  
IADJ  
390pF  
IADJ  
COSC  
ROSC  
RCS1  
51  
ISENSE+  
ISENSE+  
ROSC  
105K  
CCS  
.022mF  
RSENSE  
4mW  
ISENSE-  
CTL  
NC  
ISENSE-  
VREG  
CTL  
NC  
8
VREG  
RCS2  
51  
Input  
10K  
10K  
10K  
P1  
10K  
100K  
N1  
10mF  
10K  
Consult factory for 16 lead SO  
wide package.  
10K  
Cherry Semiconductor Corporation  
2000 South County Trail, East Greenwich, RI 02818  
Tel: (401)885-3600 Fax: (401)885-5786  
Email: info@cherry-semi.com  
Web Site: www.cherry-semi.com  
Rev. 4/21/99  
A
Company  
1
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