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BS62LV4007TIP70 PDF预览

BS62LV4007TIP70

更新时间: 2024-01-30 16:23:49
品牌 Logo 应用领域
BSI 内存集成电路静态存储器光电二极管
页数 文件大小 规格书
10页 374K
描述
Very Low Power/Voltage CMOS SRAM 512K X 8 bit

BS62LV4007TIP70 技术参数

是否Rohs认证: 符合生命周期:Obsolete
包装说明:TSOP1, TSSOP32,.8,20Reach Compliance Code:unknown
风险等级:5.84Is Samacsys:N
最长访问时间:70 nsI/O 类型:COMMON
JESD-30 代码:R-PDSO-G32长度:18.4 mm
内存密度:4194304 bit内存集成电路类型:STANDARD SRAM
内存宽度:8湿度敏感等级:3
功能数量:1端子数量:32
字数:524288 words字数代码:512000
工作模式:ASYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:512KX8
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:TSOP1封装等效代码:TSSOP32,.8,20
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE
并行/串行:PARALLEL电源:5 V
认证状态:Not Qualified座面最大高度:1.2 mm
最大待机电流:0.0008 A最小待机电流:1.5 V
子类别:SRAMs最大压摆率:0.06 mA
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子形式:GULL WING端子节距:0.5 mm
端子位置:DUAL宽度:8 mm
Base Number Matches:1

BS62LV4007TIP70 数据手册

 浏览型号BS62LV4007TIP70的Datasheet PDF文件第2页浏览型号BS62LV4007TIP70的Datasheet PDF文件第3页浏览型号BS62LV4007TIP70的Datasheet PDF文件第4页浏览型号BS62LV4007TIP70的Datasheet PDF文件第5页浏览型号BS62LV4007TIP70的Datasheet PDF文件第6页浏览型号BS62LV4007TIP70的Datasheet PDF文件第7页 
Very Low Power/Voltage CMOS SRAM  
512K X 8 bit  
BSI  
BS62LV4007  
„ FEATURES  
„ DESCRIPTION  
• Vcc operation voltage : 4.5V ~ 5.5V  
• Very low power consumption :  
The BS62LV4007 is a high performance, very low power CMOS  
Static Random Access Memory organized as 524,288 words by 8 bits  
and operates from a range of 4.5V to 5.5V supply voltage.  
Advanced CMOS technology and circuit techniques provide both high  
speed and low power features with a typical CMOS standby current of  
2.0uA at 5.0V/25oC and maximum access time of 55ns at 5.0V/85oC.  
Easy memory expansion is provided by an active LOW chip enable  
(CE) , and active LOW output enable (OE) and three-state output  
drivers.  
Vcc = 5.0V C-grade: 68mA (@55ns) operating current  
I -grade: 70mA (@55ns) operating current  
C-grade: 58mA (@70ns) operating current  
I -grade: 60mA (@70ns) operating current  
2.0uA (Typ.) CMOS standby current  
• High speed access time :  
-55  
-70  
55ns  
70ns  
The BS62LV4007 has an automatic power down feature, reducing the  
power consumption significantly when chip is deselected.  
The BS62LV4007 is available in the JEDEC standard 32L SOP, TSOP  
, PDIP, TSOP II and STSOP package.  
• Automatic power down when chip is deselected  
• Fully static operation  
• Data retention supply voltage as low as 1.5V  
• Easy expansion with CE and OE options  
• Three state outputs and TTL compatible  
„ PRODUCT FAMILY  
POWER DISSIPATION  
SPEED  
( ns )  
STANDBY  
Operating  
PKG  
PRODUCT  
FAMILY  
OPERATING  
Vcc  
( I CCSB1 , Max )  
( I CC , Max )  
TYPE  
TEMPERATURE RANGE  
55ns:4.5~5.5V  
70ns:4.5~5.5V  
Vcc =5.0V  
Vcc = 5.0V  
55ns  
Vcc =5.0V  
30uA  
70ns  
-
BS62LV4007TC  
BS62LV4007STC  
BS62LV4007SC  
BS62LV4007EC  
BS62LV4007PC  
BS62LV4007TI  
BS62LV4007STI  
BS62LV4007SI  
BS62LV4007EI  
BS62LV4007PI  
TSOP 32  
-
STSOP 32  
+0 O C to +70O  
C
C
4.5V ~ 5.5V  
4.5V ~ 5.5V  
55 / 70  
55 / 70  
68mA  
70mA  
58mA  
-
SOP 32  
-
32  
TSOP2 32  
PDIP  
-
-
TSOP 32  
-
STSOP 32  
O
40 C to +85O  
60mA  
-
60uA  
-
SOP 32  
-
TSOP2 32  
-
PDIP 32  
„ BLOCK DIAGRAM  
„ PIN CONFIGURATIONS  
A18  
A16  
A14  
A12  
A7  
1
VCC  
A15  
A17  
WE  
A13  
A8  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
2
A13  
A17  
A15  
A18  
A16  
A14  
A12  
A7  
3
4
Address  
Input  
Memory Array  
5
22  
2048  
Row  
Decoder  
A6  
6
A5  
7
A9  
2048 X 2048  
A4  
BS62LV4007SC  
BS62LV4007SI  
BS62LV4007EC  
BS62LV4007EI  
BS62LV4007PC  
BS62LV4007PI  
8
A11  
OE  
Buffer  
A3  
9
A6  
A5  
A4  
A2  
10  
11  
12  
13  
14  
15  
16  
A10  
CE  
A1  
A0  
DQ7  
DQ6  
DQ5  
DQ4  
DQ3  
2048  
DQ0  
DQ1  
DQ2  
GND  
DQ0  
DQ1  
DQ2  
DQ3  
DQ4  
DQ5  
DQ6  
DQ7  
8
Data  
Input  
Buffer  
8
Column I/O  
Write Driver  
Sense Amp  
8
8
Data  
Output  
Buffer  
256  
1
2
3
4
5
6
7
8
32  
A11  
A9  
A8  
OE  
A10  
CE  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
Column Decoder  
16  
A13  
WE  
A17  
A15  
VCC  
A18  
A16  
A14  
A12  
A7  
DQ7  
DQ6  
DQ5  
DQ4  
DQ3  
GND  
DQ2  
DQ1  
DQ0  
A0  
CE  
WE  
OE  
Control  
BS62LV4007TC  
BS62LV4007STC  
BS62LV4007TI  
BS62LV4007STI  
Address Input Buffer  
9
10  
11  
12  
13  
14  
15  
16  
Vdd  
GND  
A11 A9 A8 A3 A2 A1 A0 A10  
A6  
A5  
A4  
A1  
A2  
A3  
Brilliance Semiconductor, Inc. reserves the right to modify document contents without notice.  
Revision 1.1  
Jan. 2004  
R0201-BS62LV4007  
1

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