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5962-9161709Q9X PDF预览

5962-9161709Q9X

更新时间: 2024-02-27 07:48:54
品牌 Logo 应用领域
爱特美尔 - ATMEL 存储内存集成电路静态存储器异步传输模式ATM
页数 文件大小 规格书
27页 528K
描述
Dual-Port SRAM, 8KX16, 30ns, CMOS, DIE

5962-9161709Q9X 技术参数

生命周期:Obsolete零件包装代码:DIE
包装说明:DIE,Reach Compliance Code:unknown
ECCN代码:3A001.A.2.CHTS代码:8542.32.00.41
风险等级:5.36最长访问时间:30 ns
JESD-30 代码:X-XUUC-N内存密度:131072 bit
内存集成电路类型:DUAL-PORT SRAM内存宽度:16
功能数量:1字数:8192 words
字数代码:8000工作模式:ASYNCHRONOUS
最高工作温度:125 °C最低工作温度:-55 °C
组织:8KX16封装主体材料:UNSPECIFIED
封装代码:DIE封装形状:UNSPECIFIED
封装形式:UNCASED CHIP并行/串行:PARALLEL
认证状态:Not Qualified筛选级别:MIL-PRF-38535 Class Q
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子形式:NO LEAD端子位置:UPPER
Base Number Matches:1

5962-9161709Q9X 数据手册

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Features  
Fast Access Time: 30/45 ns  
Wide Temperature Range: -55°C to +125°C  
Separate Upper Byte and Lower Byte Control for Multiplexed Bus Compatibility  
Expandable Data Bus to 32 bits or More Using Master/Slave Chip Select When Using  
More Than One Device  
On-chip Arbitration Logic  
Versatile Pin Select for Master or Slave:  
– M/S = H for Busy Output Flag On Master  
– M/S = L for Busy Input Flag On Slave  
INT Flag for Port to Port Communication  
Full Hardware Support of Semaphore Signaling Between Ports  
Fully Asynchronous Operation From Either Port  
Battery Back-up Operation: 2V Data Retention  
TTL Compatible  
Rad. Tolerant  
High Speed  
8 Kb x 16  
Single 5V + 10% Power Supply  
QML Q and V with SMD 5962-91617  
Dual Port RAM  
Introduction  
The M67025E is a very low power CMOS dual port static RAM organized as 8192 bit  
× 16. The product is designed to be used as a stand-alone 16-bit dual port RAM or as  
a combination MASTER/SLAVE dual port for 32-bit or more width systems. The Atmel  
MASTER/SLAVE dual port approach in memory system applications results in full  
speed, error free operation without the need of an additional discrete logic.  
M67025E  
Master and slave devices provide two independent ports with separate control,  
address and I/O pins that permit independent, asynchronous access for reads and  
writes to any location in the memory. An automatic power down feature controlled by  
CS permits the on-chip circuitry of each port in order to enter a very low stand by  
power mode.  
Using an array of eight transistors (8T) memory cell, the M67025E combines an  
extremely low standby supply current (typ = 1.0 µA) with a fast access time at 30 ns  
over the full temperature range. All versions offer battery backup data retention capa-  
bility with a typical power consumption at less than 5 µW.  
For military/space applications that demand superior levels of performance and reli-  
ability the M67025E is processed according to the methods of the latest revision of the  
MIL PRF 38635 (Q and V) and/or ESA SCC 9000.  
Rev. 4146J–AERO–06/03  
1

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