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5962-8946304XC PDF预览

5962-8946304XC

更新时间: 2024-01-21 15:45:44
品牌 Logo 应用领域
爱特美尔 - ATMEL 外围集成电路
页数 文件大小 规格书
43页 1238K
描述
Math Coprocessor, CMOS, CPGA68, CERAMIC, PGA-68

5962-8946304XC 技术参数

是否Rohs认证: 不符合生命周期:Transferred
零件包装代码:PGA包装说明:PGA, PGA68,10X10
针数:68Reach Compliance Code:unknown
ECCN代码:3A001.A.2.CHTS代码:8542.31.00.01
风险等级:5.19JESD-30 代码:S-CPGA-P68
JESD-609代码:e4长度:26.92 mm
端子数量:68最高工作温度:125 °C
最低工作温度:-55 °C封装主体材料:CERAMIC, METAL-SEALED COFIRED
封装代码:PGA封装等效代码:PGA68,10X10
封装形状:SQUARE封装形式:GRID ARRAY
电源:5 V认证状态:Not Qualified
筛选级别:MIL-STD-883座面最大高度:4.82 mm
子类别:Math Processors最大压摆率:150 mA
最大供电电压:5.5 V最小供电电压:4.5 V
标称供电电压:5 V表面贴装:NO
技术:CMOS温度等级:MILITARY
端子面层:Gold (Au)端子形式:PIN/PEG
端子节距:2.54 mm端子位置:PERPENDICULAR
宽度:26.92 mmuPs/uCs/外围集成电路类型:MATH PROCESSOR, COPROCESSOR
Base Number Matches:1

5962-8946304XC 数据手册

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Features  
Eight General-purpose Floating-point Data Registers, Each Supporting a Full 80-bit  
Extended Precision Real Data Format (a 64-bit Mantissa Plus a Sign Bit, and a 15-bit  
Signed Exponent)  
A 67-bit Arithmetic Unit to Allow Very Fast Calculations with Intermediate are Precision  
Greater than the Extended Precision Format  
A 67-bit Barrel Shifter for High-speed Shifting Operations (for Normalizing etc.)  
Special-purpose Hardware for High-speed Conversion Between Single, Double, and  
Extended Formats and the Internal Extended Format  
An Independent State Machine to Control Main Processor Communication for  
Pipelined Instruction Processing  
Forty-six Instructions, Including 35 Arithmetic Operations  
Full Conformation to the IEEE 754 Standard, Including All Requirements and  
Suggestions  
Support of Functions Not Defined by the IEEE Standard, Including a Full Set of  
Trigonometric and Transcendental Functions  
Seven Data Type Types: Byte, Word and Long Integers; Single, Double, and Extended  
Precision Real Numbers; and Packed Binary Coded Decimal String Real Numbers  
Twenty-two Constants Available In The On-chip ROM, Including π, e, and Powers of 10  
Virtual Memory/Machine Operations  
CMOS  
Enhanced  
Floating-point  
Co-processor  
Efficient Mechanisms for Procedure Calls, Context Switches, and Interrupt Handling  
Fully Concurrent Instruction Execution with the Main Processor  
Fully Concurrent Instruction Execution of Multiple Floating-point Instructions  
Use with any Host Processor, on an 8-, 16- or 32-bit Data Bus  
Available in 16.67, 20, 25 and 33 MHz for Tc from -55°C to +125°C  
VCC = 5V 10%  
TS68882  
Description  
The TS68882 enhanced floating-point co-processor is a full implementation of the  
IEEE Standard for Binary Floating-Point Arithmetic (754) for use with the THOMSON  
TS68000 Family of microprocessors. It is a pin and software compatible upgrade of  
the TS68881 with optimized MPU interface that provides over 1.5 times the perfor-  
mance of the TS68881. It is implemented using VLSI technology to give systems  
designers the highest possible functionality in a physically small device.  
Intended primarily for use as a co-processor to the TS68020/68030 32-bit micropro-  
cessor units (MPUs), the TS68882 provides a logical extension to the main MPU  
integer data processing capabilities. It does this by providing a very high performance  
floating-point arithmetic unit and a set of floating-point data registers that are utilized  
in a manner that is analogous to the use of the integer data registers. The TS68882  
instruction set is a natural extension of all earlier members of the TS68000 Family, and  
supports all of the addressing modes of the host MPU. Due to the flexible bus inter-  
face of the TS68000 Family, the TS68882 can be used with any of the MPU devices of  
the TS68000 Family, and it may also be used as a peripheral to non-TS68000  
processors.  
Screening/Quality  
This product could be manufactured  
R suffix  
PGA 68  
Ceramic Pin Grid Array  
F suffix  
CQFP 68  
Ceramic Quad Flat Pack  
in full compliance with either:  
MIL-STD-883 Class B  
DESC 5962-89436  
or According to ATMEL-  
Grenoble Standards  
Rev. 2119AHIREL04/02  

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