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A29040A-55

更新时间： 2024-02-24 19:47:13

品牌	Logo	应用领域
联笙电子 - AMICC		闪存存储内存集成电路光电二极管
页数	文件大小	规格书
30页	287K
描述
512K X 8 Bit CMOS 5.0 Volt-only, Uniform Sector Flash Memory

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技术参数
数据手册

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A29040A-55 技术参数

是否Rohs认证：	不符合	生命周期：	Contact Manufacturer
包装说明：	DIP, DIP32,.6	Reach Compliance Code：	unknown
风险等级：	5.8	Is Samacsys：	N
最长访问时间：	55 ns	命令用户界面：	YES
数据轮询：	YES	耐久性：	100000 Write/Erase Cycles
JESD-30 代码：	R-PDIP-T32	长度：	41.91 mm
内存密度：	4194304 bit	内存集成电路类型：	FLASH
内存宽度：	8	功能数量：	1
部门数/规模：	8	端子数量：	32
字数：	524288 words	字数代码：	512000
工作模式：	ASYNCHRONOUS	最高工作温度：	70 °C
最低工作温度：		组织：	512KX8
封装主体材料：	PLASTIC/EPOXY	封装代码：	DIP
封装等效代码：	DIP32,.6	封装形状：	RECTANGULAR
封装形式：	IN-LINE	并行/串行：	PARALLEL
电源：	5 V	认证状态：	Not Qualified
座面最大高度：	5.334 mm	部门规模：	64K
最大待机电流：	0.000005 A	子类别：	Flash Memories
最大压摆率：	0.04 mA	最大供电电压 (Vsup)：	5.5 V
最小供电电压 (Vsup)：	4.5 V	标称供电电压 (Vsup)：	5 V
表面贴装：	NO	技术：	CMOS
温度等级：	COMMERCIAL	端子形式：	THROUGH-HOLE
端子节距：	2.54 mm	端子位置：	DUAL
切换位：	YES	类型：	NOR TYPE
宽度：	15.24 mm	Base Number Matches：	1

A29040A-55 数据手册

A29040A Series

512K X 8 Bit CMOS 5.0 Volt-only,

Uniform Sector Flash Memory

Preliminary

Features

- Embedded Program algorithm automatically writes

and verifies bytes at specified addresses

nTypical 100,000 program/erase cycles per sector

n20-year data retention at 125°C

n5.0V ± 10% for read and write operations

nAccess times:

- 55/70/90 (max.)

nCurrent:

- 20 mA typical active read current

- 30 mA typical program/erase current

- 1 mA typical CMOS standby

- Reliable operation for the life of the system

nCompatible with JEDEC-standards

- Pinout and software compatible with single-power-

supply Flash memory standard

nFlexible sector architecture

- Superior inadvertent write protection

- 8 uniform sectors of 64 Kbyte each

- Any combination of sectors can be erased

- Supports full chip erase

Polling and toggle bits

Data

- Provides a software method of detecting completion

of program or erase operations

- Sector protection:

A hardware method of protecting sectors to prevent

any inadvertent program or erase operations within

that sector

nErase Suspend/Erase Resume

- Suspends a sector erase operation to read data from,

or program data to, a non-erasing sector, then

resumes the erase operation

nEmbedded Erase Algorithms

- Embedded Erase algorithm will automatically erase

the entire chip or any combination of designated

sectors and verify the erased sectors

nPackage options

- 32-pin P-DIP, PLCC, or TSOP (Forward type)

General Description

The A29040A is a 5.0 volt-only Flash memory organized as

524,288 bytes of 8 bits each. The 512 Kbytes of data are

further divided into eight sectors of 64 Kbytes each for flexible

sector erase capability. The 8 bits of data appear on I/O0 - I/O7

while the addresses are input on A0 to A18. The A29040A is

offered in 32-pin PLCC, TSOP, and PDIP packages. This

device is designed to be programmed in-system with the

standard system 5.0 volt VCC supply. Additional 12.0 volt VPP

is not required for in-system write or erase operations.

However, the A29040A can also be programmed in standard

EPROM programmers.

The A29040A has a second toggle bit, I/O2, to indicate

whether the addressed sector is being selected for erase, and

also offers the ability to program in the Erase Suspend mode.

The standard A29040A offers access times of 55, 70 and 90

ns, allowing high-speed microprocessors to operate without

wait states. To eliminate bus contention the device has

The A29040A is entirely software command set compatible

with the JEDEC single-power-supply Flash standard.

Commands are written to the command register using

standard microprocessor write timings. Register contents

serve as input to an internal state-machine that controls the

erase and programming circuitry. Write cycles also internally

latch addresses and data needed for the programming and

erase operations. Reading data out of the device is similar to

reading from other Flash or EPROM devices.

Device programming occurs by writing the proper program

command sequence. This initiates the Embedded Program

algorithm - an internal algorithm that automatically times the

program pulse widths and verifies proper program margin.

Device erasure occurs by executing the proper erase

command sequence. This initiates the Embedded Erase

algorithm

an internal algorithm that automatically

preprograms the array (if it is not already programmed)

before executing the erase operation. During erase, the

device automatically times the erase pulse widths and

verifies proper erase margin.

separate chip enable (

), write enable (

) and output

enable (

) controls.

The device requires only a single 5.0 volt power supply for

both read and write functions. Internally generated and

regulated voltages are provided for the program and erase

operations.

PRELIMINARY

(August, 2001, Version 0.1)

AMIC Technology, Inc.

12 3 4 5 6 7...30

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