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A29010V-70U PDF预览

A29010V-70U

更新时间: 2024-01-27 21:57:04
品牌 Logo 应用领域
联笙电子 - AMICC 内存集成电路光电二极管
页数 文件大小 规格书
30页 289K
描述
Flash, 128KX8, 70ns, PDSO32, 8 X 20 MM, TSOP1-32

A29010V-70U 技术参数

是否Rohs认证: 符合生命周期:Contact Manufacturer
零件包装代码:TSOP1包装说明:TSOP1, TSSOP32,.8,20
针数:32Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.32.00.51
风险等级:5.56最长访问时间:70 ns
命令用户界面:YES数据轮询:YES
JESD-30 代码:R-PDSO-G32长度:18.4 mm
内存密度:1048576 bit内存集成电路类型:FLASH
内存宽度:8功能数量:1
部门数/规模:4端子数量:32
字数:131072 words字数代码:128000
工作模式:ASYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:128KX8
封装主体材料:PLASTIC/EPOXY封装代码:TSOP1
封装等效代码:TSSOP32,.8,20封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE并行/串行:PARALLEL
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
编程电压:5 V认证状态:Not Qualified
座面最大高度:1.2 mm部门规模:32K
最大待机电流:0.000005 A子类别:Flash Memories
最大压摆率:0.04 mA最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子形式:GULL WING
端子节距:0.5 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED切换位:YES
类型:NOR TYPE宽度:8 mm
Base Number Matches:1

A29010V-70U 数据手册

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A29010 Series  
128K X 8 Bit CMOS 5.0 Volt-only,  
Uniform Sector Flash Memory  
Preliminary  
Features  
- Embedded Program algorithm automatically writes  
and verifies bytes at specified addresses  
nTypical 100,000 program/erase cycles per sector  
n20-year data retention at 125°C  
n5.0V ± 10% for read and write operations  
nAccess times:  
- 55/70/90 (max.)  
nCurrent:  
- 20 mA typical active read current  
- 30 mA typical program/erase current  
- 1 mA typical CMOS standby  
- Reliable operation for the life of the system  
nCompatible with JEDEC-standards  
- Pinout and software compatible with single-power-  
supply Flash memory standard  
- Superior inadvertent write protection  
nFlexible sector architecture  
- 32 KbyteX4 sectors  
- Any combination of sectors can be erased  
- Supports full chip erase  
- Sector protection:  
A hardware method of protecting sectors to prevent  
any inadvertent program or erase operations within  
that sector  
n
Polling and toggle bits  
- Provides a software method of detecting completion  
of program or erase operations  
Data  
nErase Suspend/Erase Resume  
- Suspends a sector erase operation to read data  
from, or program data to, a non-erasing sector, then  
resumes the erase operation  
nEmbedded Erase Algorithms  
- Embedded Erase algorithm will automatically erase  
the entire chip or any combination of designated  
sectors and verify the erased sectors  
nPackage options  
- 32-pin P-DIP, PLCC, or TSOP(Forward type)  
General Description  
The A29010 is a 5.0 volt-only Flash memory organized as  
131,072 bytes of 8 bits each. The 128 Kbytes of data are  
further divided into four sectors for flexible sector erase  
capability. The 8 bits of data appear on I/O0 - I/O7 while the  
addresses are input on A0 to A16. The A29010 is offered in  
32-pin PLCC, TSOP, and PDIP packages. This device is  
designed to be programmed in-system with the standard  
system 5.0 volt VCC supply. Additional 12.0 volt VPP is not  
required for in-system write or erase operations. However,  
the A29010 can also be programmed in standard EPROM  
programmers.  
The A29010 has the first toggle bit, I/O6, which indicates  
whether an Embedded Program or Erase is in progress, or it  
is in the Erase Suspend. Besides the I/O6 toggle bit, the  
A29010 has a second toggle bit, I/O2, to indicate whether the  
addressed sector is being selected for erase. The A29010  
also offers the ability to program in the Erase Suspend mode.  
The standard A29010 offers access times of 55, 70 and 90  
ns allowing high-speed microprocessors to operate without  
wait states. To eliminate bus contention the device has  
The device requires only a single 5.0 volt power supply for  
both read and write functions. Internally generated and  
regulated voltages are provided for the program and erase  
operations.  
The A29010 is entirely software command set compatible  
with the JEDEC single-power-supply Flash standard.  
Commands are written to the command register using  
standard microprocessor write timings. Register contents  
serve as input to an internal state-machine that controls the  
erase and programming circuitry. Write cycles also internally  
latch addresses and data needed for the programming and  
erase operations. Reading data out of the device is similar to  
reading from other Flash or EPROM devices.  
Device programming occurs by writing the proper program  
command sequence. This initiates the Embedded Program  
algorithm - an internal algorithm that automatically times the  
program pulse widths and verifies proper program margin.  
Device erasure occurs by executing the proper erase  
command sequence. This initiates the Embedded Erase  
algorithm  
-
an internal algorithm that automatically  
preprograms the array (if it is not already programmed)  
before executing the erase operation. During erase, the  
device automatically times the erase pulse widths and  
verifies proper erase margin.  
separate chip enable (  
), write enable (  
) and output  
WE  
CE  
enable (  
) controls.  
OE  
PRELIMINARY  
(August, 2001, Version 0.3)  
1
AMIC Technology, Inc.  

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