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27C4096 PDF预览

27C4096

更新时间: 2022-11-27 08:43:58
品牌 Logo 应用领域
超微 - AMD 可编程只读存储器电动程控只读存储器
页数 文件大小 规格书
12页 159K
描述
4 Megabit (256 K x 16-Bit) CMOS EPROM

27C4096 数据手册

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FINAL  
Am27C4096  
4 Megabit (256 K x 16-Bit) CMOS EPROM  
DISTINCTIVE CHARACTERISTICS  
Fast access time  
Single +5 V power supply  
— Speed options as fast as 90 ns  
Low power consumption  
— 100 µA maximum CMOS standby current  
JEDEC-approved pinout  
— Plug-in upgrade of 1 Mbit and 2 Mbit EPROMs  
— 40-pin DIP/PDIP  
±10% power supply tolerance standard  
100% Flashrite programming  
Typical programming time of 32 seconds  
Latch-up protected to 100 mA from –1 V to  
VCC + 1 V  
High noise immunity  
— 44-pin PLCC  
GENERAL DESCRIPTION  
The Am27C4096 is a 4 Mbit, ultraviolet erasable pro-  
grammable read-only memory. It is organized as 256  
Kwords, operates from a single +5 V supply, has a  
static standby mode, and features fast single address  
location programming. The Am27C4096 is ideal for use  
in 16-bit microprocessor systems. The device is avail-  
able in windowed ceramic DIP packages, and plastic  
one time programmable (OTP) PDIP and PLCC pack-  
ages.  
thus eliminating bus contention in a multiple bus micro-  
processor system.  
AMD’s CMOS process technology provides high  
speed, low power, and high noise immunity. Typical  
power consumption is only 125 mW in active mode,  
and 125 µW in standby mode.  
All signals are TTL levels, including programming sig-  
nals. Bit locations may be programmed singly, in  
blocks, or at random. The device supports AMD’s  
Flashrite programming algorithm (100 µs pulses), re-  
sulting in a typical programming time of 32 seconds.  
Data can be typically accessed in less than 90 ns, al-  
lowing high-performance microprocessors to operate  
without any WAIT states. The device offers separate  
Output Enable (OE#) and Chip Enable (CE#) controls,  
BLOCK DIAGRAM  
V
Data Outputs  
DQ0–DQ15  
CC  
V
V
SS  
PP  
Output Enable  
Chip Enable  
and  
OE#  
Output  
Buffers  
CE#/PGM#  
Prog Logic  
Y
Y
Gating  
Decoder  
A0–A17  
Address  
Inputs  
4,194,304  
Bit Cell  
Matrix  
X
Decoder  
11408F-1  
Publication# 11408 Rev: F Amendment/0  
Issue Date: May 1998  

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