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27C020 PDF预览

27C020

更新时间: 2022-12-09 08:49:38
品牌 Logo 应用领域
超微 - AMD 可编程只读存储器电动程控只读存储器
页数 文件大小 规格书
12页 165K
描述
2 Megabit (256 K x 8-Bit) CMOS EPROM

27C020 数据手册

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FINAL  
Am27C020  
2 Megabit (256 K x 8-Bit) CMOS EPROM  
DISTINCTIVE CHARACTERISTICS  
Fast access time  
Single +5 V power supply  
— Speed options as fast as 55 ns  
Low power consumption  
±10% power supply tolerance standard  
100% Flashrite™ programming  
Typical programming time of 32 seconds  
— 100 µA maximum CMOS standby current  
JEDEC-approved pinout  
Latch-up protected to 100 mA from –1 V to  
VCC + 1 V  
— Plug in upgrade of 1 Mbit EPROM  
— Easy upgrade from 28-pin JEDEC EPROMs  
High noise immunity  
Compact 32-pin DIP, PDIP, and PLCC packages  
GENERAL DESCRIPTION  
The Am27C020 is a 2 Megabit, ultraviolet erasable pro-  
grammable read-only memory. It is organized as 256  
Kwords by 8 bits per word, operates from a single +5 V  
supply, has a static standby mode, and features fast  
single address location programming. Products are  
available in windowed ceramic DIP packages, as well  
as plastic one time programmable (OTP) PDIP and  
PLCC packages.  
thus eliminating bus contention in a multiple bus micro-  
processor system.  
AMD’s CMOS process technology provides high  
speed, low power, and high noise immunity. Typical  
power consumption is only 100 mW in active mode,  
and 100 µW in standby mode.  
All signals are TTL levels, including programming sig-  
nals. Bit locations may be programmed singly, in  
blocks, or at random. The device supports AMD’s  
Flashrite programming algorithm (100 µs pulses), re-  
sulting in a typical programming time of 32 seconds.  
Data can be typically accessed in less than 55 ns, al-  
lowing high-performance microprocessors to operate  
without any WAIT states. The device offers separate  
Output Enable (OE#) and Chip Enable (CE#) controls,  
BLOCK DIAGRAM  
V
Data Outputs  
DQ0–DQ7  
CC  
V
V
SS  
PP  
Output Enable  
Chip Enable  
and  
OE#  
CE#  
Output  
Buffers  
Prog Logic  
PGM#  
Y
Y
Gating  
Decoder  
A0–A17  
Address  
Inputs  
2,097,152  
Bit Cell  
Matrix  
X
Decoder  
11507H-1  
Publication# 11507 Rev: H Amendment/0  
Issue Date: May 1998  

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