Advance information
AS4LC2M8S1
AS4LC1M16S1
3.3V 2M × 8/ 1M × 16 CMOS synchronous DRAM
Features
• Organization
- 1,048,576 words × 8 bits × 2 banks (2M × 8)
11 row, 9 column address
- 524,288 words × 16 bits × 2 banks (1M × 16)
11 row,8 column address
• All signals referenced to positive edge of clock, fully
synchronous
• Dual internal banks controlled by A11 (bank select)
• High speed
- 143/ 125/ 100 MHz
- 7/ 8/ 10 ns clock access time
• Low power consumption
- Active: 576 mW max
- Standby: 7.2 mW max, CMOS I/ O
• 2048 refresh cycles, 64 ms refresh interval
• Auto refresh and self refresh (2K self refresh mode at 64 ms)
• PC100 functionality
• Automatic and direct precharge including concurrent
autoprecharge
• Burst read, write/ Single write
• Random column address assertion in every cycle, pipelined
operation
• LVTTL compatible I/ O
• 3.3V power supply
• JEDEC standard package, pinout and function
- 400 mil, 44-pin TSOP II (2M × 8)
- 400 mil, 50-pin TSOP II (1M × 16)
• Read/ write data masking
• Programmable burst length (1/ 2/ 4/ 8/ full page)
• Programmable burst sequence (sequential/ interleaved)
• Programmable CAS latency (1/ 2/ 3)
Pin arrangement
Pin designation
TSOP II
50
TSOP II
Pin(s)
Description
V
V
SS
V
V
SS
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
1
CC
CC
DQ0
DQ1
49
48
47
46
45
44
43
42
41
40
39
38
37
36
DQ15
DQ14
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
DQ0
2
DQ7
DQM (2M × 8)
UDQM/ LDQM (1M × 16)
V
V
3
SSQ
SSQ
Output disable/ write mask
V
V
SSQ
SSQ
DQ6
4
DQ1
DQ13
DQ12
V
V
DQ2
DQ3
5
CCQ
CCQ
RA0 – 10
Address inputs CA0 – 7 (×16)
CA0 – 8 (×8)
DQ2
6
DQ5
V
V
V
V
CCQ
DQ4
DQ5
CCQ
7
SSQ
SSQ
A0 to A10
A11
DQ11
DQ10
DQ3
8
DQ4
V
V
CCQ
NC
9
CCQ
V
V
NC
NC
DQM
CLK
10
11
12
13
14
15
16
17
18
19
20
21
22
SSQ
SSQ
DQ6
DQ7
DQ9
DQ8
NC
WE
CAS
Bank address (BA)
V
V
CCQ
CCQ
DQ0 to DQ7 (2M × 8)
DQ0 to DQ15 (1M × 16)
Input/ output
LDQM
NC
UDQM
CLK
CKE
NC
A9
A8
A7
A6
A5
RAS
CS
A11
A10
A0
A1
A2
A3
CKE
NC
A9
A8
A7
A6
A5
A4
V
SS
WE
CAS
RAS
CS
A11
A10
A0
A1
A2
A3
35
34
33
32
31
30
29
RAS
CAS
Row address strobe
Column address strobe
Write enable
WE
V
CC
CS
Chip select
23
24
25
28
27
26
A4
V
SS
VCC, VCCQ
Power (3.3V ± 0.3V)
Ground
V
CC
VSS, V
LEGEND
2M × 8
1M × 16
512K × 16 × 2 banks
2K
2K (A0 – A10)
2 (BA)
SSQ
Configuration
Refresh Count
Row Address
1M × 8 × 2 banks
2K
2K (A0 – A10)
2 (BA)
CLK
CKE
Clock input
Clock enable
Bank Address
Column Address
512 (A0 – A8)
256 (A0 – A7)
Selection guide
Symbol
fMax
tAC
–7
143
5.5
2
–8
125
6
–10
100
6
Unit
MHz
ns
Bus frequency (CL = 3)
Maximum clock access time (CL = 3)
Minimum input setup time
tS
2
2
ns
Minimum input hold time
tH
1.0
70
1.0
80
1.0
80
ns
Row cycle time (CL = 3, BL = 1)
tRC
ns
Maximum operating current ([×16], RD or
WR, CL = 3), BL = 2
ICC1
130
1
100
1
100
1
mA
mA
Maximum CMOS standby current, self refresh
ICC6
7/ 5/ 00
ALLIANCE SEMICONDUCTOR
1
Copyright ©2000 Alliance Semiconductor. All rights reserved.
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