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AS29LL200B-70SI PDF预览

AS29LL200B-70SI

更新时间: 2024-01-19 18:06:19
品牌 Logo 应用领域
ALSC /
页数 文件大小 规格书
20页 189K
描述
Flash Memory

AS29LL200B-70SI 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:,Reach Compliance Code:unknown
风险等级:5.92Base Number Matches:1

AS29LL200B-70SI 数据手册

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3UHOLPLQDU\#LQIRUPDWLRQ  
$65<)533  
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89#589;245;49#&026#)ODVK#((3520  
)HDWXUHV  
• Organization: 256K×8 or 128K×16  
Sector architecture  
Low power consumption  
- 20 mA typical read current  
- One 16K; two 8K; one 32K; and three 64K byte sectors  
- Boot code sector architecture—T (top) or B (bottom)  
- Erase any combination of sectors or full chip  
Single 5.0±0.5V power supply for read/ write operations  
Sector protection  
• High speed 55/ 70/ 90/ 120 ns address access time  
Automated on-chip programming algorithm  
- Automatically programs/ verifies data at specified ad-  
dress  
Automated on-chip erase algorith  
- Automatically preprograms/ erases chip or specified sec-  
tors  
• 10,000 write/ erase cycle endurance  
• Hardware RESET pin  
- 30 mA typical program current  
- 300 µA typical standby current  
- 1 µA typical standby current (RESET = 0)  
JEDEC standard software, packages and pinouts  
- 48-pin TSOP  
- 44-pin SO  
• Detection of program/ erase cycle completion  
- DQ7 DATApolling  
- DQ6 toggle bit  
- RY/ BY output  
Erase suspend/ resume  
- Supports reading data from a sector not being erased  
Low V write lock-out below 2.8V  
CC  
- Resets internal state machine to read mode  
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3LQ#DUUDQJHPHQW  
48-pin TSOP  
44-pin SO  
Sector protect  
switches  
RY/ BY  
DQ0–DQ15  
V
CC  
V
SS  
NC  
RY/ BY  
NC  
1
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
RESET  
WE  
A8  
Erase voltage  
generator  
Input/ output  
buffers  
2
RESET  
3
A7  
4
A9  
Program/ erase  
control  
WE  
BYTE  
A6  
5
A10  
A11  
A12  
A13  
A14  
A15  
A16  
BYTE  
A5  
6
A4  
7
Program voltage  
generator  
AS29F200  
Command  
register  
A3  
8
A2  
A1  
A0  
CE  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
STB  
Chip enable  
Output enable  
Logic  
Data latch  
CE  
OE  
A-1  
V
V
SS  
SS  
OE  
DQ0  
DQ15/ A-1  
DQ7  
Y decoder  
Y gating  
STB  
DQ8  
DQ14  
DQ6  
DQ1  
DQ9  
DQ13  
DQ5  
V
detector  
Timer  
CC  
DQ2  
X decoder  
Cell matrix  
DQ10  
DQ3  
DQ12  
DQ4  
A0A16  
DQ11  
V
CC  
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29F200-55 29F200-70 29F200-90 29F200-120 Unit  
Maximum access time  
tAA  
tCE  
tOE  
55  
55  
25  
70  
70  
30  
90  
90  
35  
120  
120  
50  
ns  
ns  
ns  
Maximum chip enable access time  
Maximum output enable access time  
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Copyright ©1998 Alliance Semiconductor. All rights reserved.  

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