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ATS682LSHTN-T PDF预览

ATS682LSHTN-T

更新时间: 2024-01-06 19:57:46
品牌 Logo 应用领域
急速微 - ALLEGRO 传感器换能器磁场传感器信息通信管理
页数 文件大小 规格书
16页 318K
描述
Miniature, Two-Wire, True Zero Speed Differential Peak-Detecting Sensor IC

ATS682LSHTN-T 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active包装说明:SIP4,.18,50
Reach Compliance Code:compliant风险等级:1.71
Is Samacsys:N外壳:PLASTIC
JESD-609代码:e3最大磁场范围:100 mT
最小磁场范围:3 mT安装特点:THROUGH HOLE MOUNT
端子数量:4最大工作电流:16.8 mA
最高工作温度:150 °C最低工作温度:-40 °C
输出接口类型:2-WIRE INTERFACE输出类型:DIGITAL CURRENT
封装主体材料:PLASTIC/EPOXY封装等效代码:SIP4,.18,50
封装形状/形式:CYLINDRICAL电源:4/24 V
传感器/换能器类型:MAGNETIC FIELD SENSOR,HALL EFFECT子类别:Other Sensors/Transducers
最大供电电压:24 V最小供电电压:4 V
表面贴装:NO技术:BICMOS
端子面层:Matte Tin (Sn)端接类型:SOLDER
Base Number Matches:1

ATS682LSHTN-T 数据手册

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ATS682LSH  
Miniature, Two-Wire, True Zero Speed  
Differential Peak-Detecting Sensor IC  
Features and Benefits  
Description  
The ATS682LSH is a Hall-effect integrated circuit and rare  
earth pellet combination that provides a user-friendly solution  
for true zero-speed digital gear-tooth sensing in two-wire  
applications. This small package, with an optimized two-wire  
leadframe, can be easily assembled and used in conjunction  
with a wide variety of gear shapes and sizes.  
True zero-speed operation  
Automatic Gain Control (AGC) for air gap independent  
switchpoints  
Automatic Offset Adjustment (AOA) for signal processing  
optimization  
Running-mode calibration for continuous optimization  
Precise duty cycle over operating temperature range  
Internal current regulator for two-wire operation  
Undervoltage lockout  
On-chip voltage regulator with wide operating voltage  
range and stability in the presence of a variety of complex  
load impedances  
The integrated circuit incorporates a dual-element Hall-effect  
circuit and signal processing that switches in response to  
differential magnetic signals created by ferrous gear teeth.  
The circuitry contains a sophisticated digital circuit that  
reduces magnet and system offsets, calibrates the gain for air  
gap independent switchpoints and provides true zero-speed  
operation.  
Single chip IC for high reliability  
Package: 4-pin SIP (suffix SH)  
Signaloptimizationoccursatpower-upthroughtheadjustment  
ofoffsetandgainandisandismaintainedthroughoutoperation  
with the use of a running-mode calibration scheme. Running-  
modecalibrationprovidesimmunityfromenvironmentaleffects  
such as micro-oscillations of the sensed target or sudden air  
gap changes.  
Theregulatedcurrentoutputisconfiguredfortwo-wireinterface  
circuitryandisideallysuitedforobtainingspeedinformationin  
wheelspeedapplications.TheHallelementspacingisoptimized  
for high resolution, small diameter targets. The package is lead  
(Pb) free, with 100% matte tin lead frame plating.  
Not to scale  
Functional Block Diagram  
VCC  
Hall  
Amplifier  
Gain  
Automatic Offset  
AOA DAC  
AGC DAC  
Internal Regulator  
Control  
Gain Control  
Tracking  
DAC  
Peak Hold  
GND  
Test  
Test Signals  
ATS682-DS, Rev. 2  

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