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A6B273KLW-T PDF预览

A6B273KLW-T

更新时间: 2024-02-17 11:33:46
品牌 Logo 应用领域
急速微 - ALLEGRO 外围驱动器驱动程序和接口接口集成电路光电二极管
页数 文件大小 规格书
10页 591K
描述
8-BIT LATCHED DMOS POWER DRIVER

A6B273KLW-T 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP,
针数:20Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.83Is Samacsys:N
接口集成电路类型:LATCH BASED PERIPHERAL DRIVERJESD-30 代码:R-PDSO-G20
JESD-609代码:e3长度:12.8 mm
功能数量:8端子数量:20
最高工作温度:125 °C最低工作温度:-40 °C
输出电流流向:SINK标称输出峰值电流:0.5 A
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
认证状态:Not Qualified座面最大高度:2.65 mm
最大供电电压:5.5 V最小供电电压:4.5 V
标称供电电压:5 V表面贴装:YES
技术:NMOS温度等级:AUTOMOTIVE
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
宽度:7.5 mmBase Number Matches:1

A6B273KLW-T 数据手册

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6B273  
8-BIT LATCHED  
DMOS POWER DRIVER  
The A6B273KA and A6B273KLW combine eight (positive-edge-  
triggered D-type) data latches and DMOS outputs for systems requiring  
relatively high load power. Driver applications include relays, sole-  
noids, and other medium-current or high-voltage peripheral power  
loads. The CMOS inputs and latches allow direct interfacing with  
microprocessor-based systems. Use with TTL may require appropriate  
pull-up resistors to ensure an input logic high.  
LOGIC  
SUPPLY  
20  
19  
18  
17  
16  
15  
14  
13  
1
2
3
4
CLEAR  
V
DD  
IN  
8
IN  
IN  
1
IN  
7
2
OUT  
OUT  
1
8
OUT  
OUT  
OUT  
OUT  
OUT  
IN  
5
6
7
6
5
2
3
4
3
4
The DMOS output inverts the DATA input. All of the output  
drivers are disabled (the DMOS sink drivers turned OFF) with the  
CLEAR input low. The A6B273KA/KLW DMOS open-drain outputs  
are capable of sinking up to 500 mA. Similar devices with reduced  
rDS(on) are available as the A6273KA/KLW.  
7
8
OUT  
IN  
6
9
12  
11  
IN  
IN  
5
10  
GROUND  
STROBE  
The A6B273KA is furnished in a 20-pin dual in-line plastic  
package. The A6B273KLW is furnished in a 20-lead wide-body,  
small-outline plastic package (SOIC) with gull-wing leads for surface-  
mount applications. Copper lead frames, reduced supply current  
requirements, and low on-state resistance allow both devices to sink  
150 mA from all outputs continuously, to ambient temperatures over  
85°C.  
Dwg. PP-015-2A  
Note that the A6B273KA (DIP) and the A6B273KLW  
(SOIC) are electrically identical and share a common  
terminal number assignment.  
ABSOLUTE MAXIMUM RATINGS  
at TA = 25°C  
FEATURES  
Output Voltage, VO ............................... 50 V  
Output Drain Current,  
50 V Minimum Output Clamp Voltage  
150 mA Output Current (all outputs simultaneously)  
5 Typical rDS(on)  
Continuous, IO .......................... 150 mA*  
Peak, IOM ................................... 500 mA†  
Single-Pulse Avalanche Energy,  
EAS ................................................. 30 mJ  
Logic Supply Voltage, VDD .................. 7.0 V  
Input Voltage Range,  
Low Power Consumption  
Replacements for TPIC6B273N and TPIC6B273DW  
VI ................................... -0.3 V to +7.0 V  
Selection Guide  
Package Power Dissipation,  
PD ........................................... See Graph  
Operating Temperature Range,  
TA ................................. -40°C to +125°C  
Storage Temperature Range,  
RθJC  
(°C/W)  
17  
RθJA  
(°C/W)  
70  
Part Number Pb-free*  
Package  
Packing  
A6B273KLW-T  
A6B273KLWTR-T  
Yes  
Yes  
20-pin SOICW  
20-pin SOICW 1000 per reel  
37 per tube  
17  
70  
*Pb-based variants are being phased out of the product line. Some variants cited in  
this footnote are in production but have been determined to be LAST TIME BUY or  
TS ................................. -55°C to +150°C  
* Each output, all outputs on.  
NOT FOR NEW DESIGN.  
This classification indicates that sale of this device is currently  
restricted to existing customer applications. The variants should not be purchased for new  
design applications because obsolescence in the near future is probable. Samples are no  
longer available. Status change for LAST TIME BUY: October 31, 2006. Deadline for  
receipt of LAST TIME BUY orders: April 27, 2007. These variants include: A6B273KLW and  
A6B273KLWTR. Status change for NOT FOR NEW DESIGN: May 1, 2006. These variants  
include: A6B273KA.  
† Pulse duration 100 µs, duty cycle 2%.  
Caution: These CMOS devices have input static  
protection (Class 3) but are still susceptible to damage if  
exposed to extremely high static electrical charges.  

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