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A3961SB PDF预览

A3961SB

更新时间: 2024-02-01 16:07:14
品牌 Logo 应用领域
急速微 - ALLEGRO 驱动器光电二极管电动机控制
页数 文件大小 规格书
10页 92K
描述
DUAL FULL-BRIDGE PWM MOTOR DRIVER

A3961SB 技术参数

生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP,针数:24
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.57
Is Samacsys:N模拟集成电路 - 其他类型:STEPPER MOTOR CONTROLLER
JESD-30 代码:R-PDSO-G24长度:15.4 mm
功能数量:1端子数量:24
最高工作温度:85 °C最低工作温度:-20 °C
最大输出电流:0.8 A封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE认证状态:Not Qualified
座面最大高度:2.65 mm最大供电电压 (Vsup):5.25 V
最小供电电压 (Vsup):4.75 V标称供电电压 (Vsup):5 V
表面贴装:YES温度等级:OTHER
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL宽度:7.5 mm
Base Number Matches:1

A3961SB 数据手册

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3961  
DUAL FULL-BRIDGE PWM MOTOR DRIVER  
Designed for pulse-width modulated (PWM) current control of  
bipolar stepper motors, the A3961S— is capable of continuous output  
24  
23  
OUT  
2B  
1
OUT  
currents to ±800 mA and operating voltages to 45 V. Internal fixed  
off-time PWM current-control circuitry can be used to regulate the  
maximum load current to a desired value. An internal precision voltage  
reference is provided to improve motor peak current control accuracy.  
The peak load current limit is set by the user’s selection of an external  
resistor divider and current-sensing resistors.  
1B  
E 2  
2
3
4
5
E1  
22 SENSE2  
SENSE1  
OUT1A  
VBB1  
21  
OUT  
2A  
20  
VBB2  
GROUND  
6
7
19  
18  
17  
16  
15  
14  
13  
GROUND  
GROUND  
GROUND  
I FULL/PD  
The fixed off-time pulse duration is set by user-selected external  
RC timing networks. The capacitor in the RC timing network also  
determines a user-selectable blanking window that prevents false  
triggering of the PWM current control circuitry during switching transi-  
tions. This eliminates the need for two external RC filter networks on  
the current-sensing comparator inputs.  
8
9
V
REFOUT  
V
REFIN  
VCC  
10  
11  
RC1  
RC2  
PHASE1  
PHASE2  
ENABLE2  
12  
ENABLE1  
For each bridge the PHASE input controls load current polarity by  
selecting the appropriate source and sink driver pair. For each bridge  
the ENABLE input, when held high, disables the output drivers. Special  
power-up sequencing is not required. Internal circuit protection includes  
thermal shutdown with hysteresis, transient-suppression diodes, and  
crossover-current protection.  
Note the A3961SB (DIP) and the A3961SLB  
(SOIC) are electrically identical and share a  
common terminal number assignment.  
ABSOLUTE MAXIMUM RATINGS  
Load Supply Voltage, VBB . . . . . . . . . . 45 V  
Output Current, IOUT . . . . . . . . . . ±800 mA*  
Logic Supply Voltage, VCC . . . . . . . . . 7.0 V  
The A3961S— is supplied in a choice of two power packages:  
24-pin dual-in-line plastic package with copper heat-sink tabs and  
24-lead plastic SOIC with copper heat-sink tabs. In both packages the  
power tab is at ground potential and needs no electrical isolation.  
Logic Input Voltage Range,  
VIN . . . . . . . . . . . -0.3 V to VCC + 0.3 V  
Sense Voltage, VSENSE . . . . . . . . . . . . 1.0 V  
FEATURES  
Reference Output Current,  
IREF OUT . . . . . . . . . . . . . . . . . . . 1.0 mA  
±800 mA Continuous Output Current Rating  
45 V Output Voltage Rating  
Internal PWM Current Control, Saturated Sink Drivers  
Internally Generated Precision 2.5 V Reference  
Internal Transient-Suppression Diodes  
Internal Thermal-Shutdown Circuitry  
Package Power Dissipation,  
PD . . . . . . . . . . . . . . . . . . . . See Graph  
Operating Temperature Range,  
TA . . . . . . . . . . . . . . . . . -20˚C to +85˚C  
Junction Temperature, TJ . . . . . . . +150˚C†  
Storage Temperature Range,  
Crossover-Current Protection, UVLO Protection  
TS . . . . . . . . . . . . . . . . -55˚C to +150˚C  
* Output current rating may be limited by duty  
cycle, ambient temperature, and heat sinking.  
Under any set of conditions, do not exceed the  
specified current rating or a junction tempera-  
ture of 150˚C.  
Always order by complete part number:  
PART NUMBER  
PACKAGE  
RθJA  
RθJT  
† Fault conditions that produce excessive  
junction temperature will activate device  
thermal shutdown circuitry. These conditions  
can be tolerated but should be avoided.  
A3961SB  
24-Pin DIP  
40°C/W  
6°C/W  
A3961SLB  
24-Lead SOIC  
55°C/W  
6°C/W  

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