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HPFC-5100C PDF预览

HPFC-5100C

更新时间: 2024-01-18 03:08:51
品牌 Logo 应用领域
安捷伦 - AGILENT 光纤微控制器和处理器外围集成电路uCs集成电路uPs集成电路PC
页数 文件大小 规格书
4页 170K
描述
Tachyon TL 33 MHz PCI to Fibre Channel Controller

HPFC-5100C 技术参数

生命周期:Obsolete包装说明:,
Reach Compliance Code:unknownHTS代码:8542.31.00.01
风险等级:5.82Is Samacsys:N
JESD-30 代码:S-PBGA-B272端子数量:272
封装主体材料:PLASTIC/EPOXY封装形状:SQUARE
封装形式:GRID ARRAY认证状态:Not Qualified
表面贴装:YES技术:CMOS
端子形式:BALL端子位置:BOTTOM
uPs/uCs/外围集成电路类型:MICROPROCESSOR CIRCUITBase Number Matches:1

HPFC-5100C 数据手册

 浏览型号HPFC-5100C的Datasheet PDF文件第2页浏览型号HPFC-5100C的Datasheet PDF文件第3页浏览型号HPFC-5100C的Datasheet PDF文件第4页 
Tachyon TL  
33 MHz PCI to Fibre Channel  
Controller  
Technical Data  
HPFC-5100C  
Features  
assurance of interoperability and  
true Fibre Channel performance.  
• Second Generation Controller  
IC, Based on TACHYON  
Family Architecture  
Tachyon TL focuses on mass  
storage applications for any  
topology that require Class 3 and  
2 (via software) and SCSI upper  
layer protocol handling. Coupled  
with a high performance 33 MHz,  
32/64-bit PCI bus interface,  
Tachyon TL provides a cost-  
effective, high-performance mass  
storage solution.  
• Supports All Fibre Channel  
Topologies; Arbitrated Loop  
(FC-AL) and N_Port Fabric  
Attachment  
• Supports Both Class 3 and  
Class 2 (via Software)  
• 33 MHz, 32/64-Bit PCI  
Interface  
head, coupled with the highest  
levels of parallelism to provide  
maximum I/O rates and  
bandwidth.  
• 1 Gigabit/Second Fibre  
Channel Rate  
TACHYON Architecture  
Tachyon TL continues with the  
TACHYON architecture, a  
• Full Duplex Support with  
Parallel Inbound and  
Outbound Processing  
• 32/64-Bit PCI Interface,  
Compliant to PCI v2.1  
• Complete Hardware Handling  
of Entire SCSI I/O via FCP  
On-Chip Assists  
FC-AL Features  
complete hardware-based state  
machine design. This architec-  
ture does not require an addi-  
tional on-board microprocessor  
and therefore avoids reduced  
performance issues relating to  
processor cycles per second and  
access time to firmware. Rather,  
the TACHYON architecture is  
designed to be a single chip Fibre  
Channel solution.  
In addition to the high-perfor-  
mance architecture, Tachyon TL  
offers FC-AL-1 Fibre Channel  
features, such as Auto Status,  
multiple I/Os in the same loop  
arbitration cycle, loop map, loop  
broadcast, and loop directed  
reset. These features allow the  
designer to achieve higher  
performance in an arbitrated loop  
topology.  
• Full Initiator and Target  
Mode Functionality  
Applications  
• Motherboard Integration  
• Host-Based Adapters  
• Storage Sub-systems  
Tachyon TL provides the highest  
levels of concurrency via  
numerous independent functional  
blocks providing parallel  
processing of data, control, and  
commands. In addition, these  
blocks process at hardware  
speeds versus firmware speeds,  
and automate the entire SCSI I/O  
in hardware. The result is  
Physical Layer  
The physical layer interface is the  
popular 10-bit wide specification  
that allows interfacing to a low-  
cost serializer/deserializer  
(SerDes) IC. This is the same  
physical layer interface that is  
popular on Fibre Channel disk  
drives today due to its quality  
gigabit signaling, small form  
factor, and low cost.  
• I O Designs  
2
Description  
The HPFC-5100C, Tachyon TL, is  
a second-generation controller that  
leverages extensive experience in  
Fibre Channel, established with the  
original TACHYON controller.  
Tachyon TL carries forward the  
minimized latency and I/O over-  

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