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HDMP-1636A PDF预览

HDMP-1636A

更新时间: 2024-02-03 22:50:24
品牌 Logo 应用领域
安捷伦 - AGILENT 网络接口光纤电信集成电路电信电路以太网以太网:16GBASE-T
页数 文件大小 规格书
18页 284K
描述
Gigabit Ethernet and Fibre Channel SerDes ICs

HDMP-1636A 技术参数

是否Rohs认证: 符合生命周期:Obsolete
包装说明:10 MM, LEAD FREE, PLASTIC, QFP-64Reach Compliance Code:compliant
风险等级:5.66数据速率:1250000 Mbps
JESD-30 代码:S-PQFP-G64JESD-609代码:e3
长度:10 mm功能数量:1
端子数量:64收发器数量:1
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:FQFP
封装等效代码:QFP64,.51SQ,20封装形状:SQUARE
封装形式:FLATPACK, FINE PITCH峰值回流温度(摄氏度):260
电源:3.3 V认证状态:Not Qualified
座面最大高度:2.45 mm子类别:Network Interfaces
标称供电电压:3.3 V表面贴装:YES
电信集成电路类型:ETHERNET TRANSCEIVER温度等级:COMMERCIAL
端子面层:MATTE TIN (394)端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:10 mm
Base Number Matches:1

HDMP-1636A 数据手册

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Gigabit Ethernet and  
Fibre Channel SerDes ICs  
HDMP-1636A Transceiver  
HDMP-1646A Transceiver  
HDMP-T1636A Transceiver  
Technical Data  
Features  
• IEEE 802.3z Gigabit Ethernet  
Compatible  
• ANSI x3.230-1994 Fibre  
Channel Compatible (FC-O)  
• Supports Serial Data Rates of  
1062.5 MBd (Fibre Channel)  
& 1250 MBd (Gigabit  
Ethernet)  
• Low Power Consumption,  
630 mW Typical  
• Transmitter and Receiver  
Functions Incorporated onto  
a Single IC  
• Three Package Sizes  
Available:  
– 10 mm TQFP (HDMP-T1636A)  
– 10 mm PQFP (HDMP-1636A)  
– 14 mm PQFP (HDMP-1646A)  
Description  
The HDMP-1636A/46A/T1636A  
transceiver is a single integrated  
circuit packaged in a plastic QFP  
package. It provides a low-cost,  
low-power physical layer solution  
for 1250 MBd Gigabit Ethernet,  
1062.5 MBd Fibre Channel, and  
proprietary link interfaces. It  
provides complete Serialize/  
Deserialize (SerDes) for copper  
transmission, incorporating the  
Gigabit Ethernet/Fibre Channel  
transmit and receive functions  
into a single device.  
The transmitter section’s PLL  
locks to the user supplied  
reference byte clock. This clock  
is then multiplied by 10 to gener-  
ate the high speed serial clock  
used to generate the high speed  
output. The high speed outputs  
are capable of interfacing directly  
to copper cables for electrical  
transmission or to a separate  
fiber optic module for optical  
transmission.  
This chip is used to build a high  
speed interface (as shown in  
Figure 1) while minimizing board  
space, power and cost. It is  
compatible with the IEEE 802.3z  
specification.  
• 10-Bit Wide Parallel TTL  
Compatible I/Os  
• Single +3.3 V Power Supply  
• 5-Volt Tolerant I/Os  
• 2 kV ESD Protection on All  
Pins  
The transmitter section accepts  
10-bit wide parallel TTL data and  
serializes this data into a high  
speed serial data stream. The  
parallel data is expected to be  
“8B/10B” encoded data, or equiv-  
alent. This parallel data is latched  
into the input register of the  
transmitter section on the rising  
edge of the reference clock (used  
as the transmit byte clock). A  
1062.5 MHz reference clock is  
used in Fibre Channel operation,  
whereas a 125 MHz reference  
clock is used in Gigabit Ethernet  
operation.  
The receiver section accepts a  
serial electrical data stream at  
1062.5 MBd or 1250 MBd and  
recovers the original 10-bit wide  
parallel data. The receiver PLL  
locks onto the incoming serial  
signal and recovers the high  
speed serial clock and data. The  
serial data is converted back into  
10-bit parallel data, recognizing  
the 8B/10B comma character to  
establish byte alignment.  
Applications  
• 1250 MBd Gigabit Ethernet  
Interface  
• 1062.5 MBd Fibre Channel  
Interface  
• Mass Storage System I/O  
Channel  
• Work Station/Server I/O  
Channel  
• Backplane Serialization  
• FC Interface for Disk Drives  
and Arrays  
CAUTION: As with all semiconductor ICs, it is advised that normal static precautions be taken in handling and assembly  
of this component to prevent damage and/or degradation which may be induced by electrostatic discharge (ESD).  

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