Datasheet > 5962R9583403QXA

5962R9583403QXA

更新时间： 2024-02-09 07:21:02

品牌	Logo	应用领域
艾法斯 - AEROFLEX		接收机
页数	文件大小	规格书
11页	81K
描述
Quad Receiver

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技术参数
数据手册

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5962R9583403QXA 技术参数

生命周期：	Obsolete	包装说明：	DFP,
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.63
Is Samacsys：	N	输入特性：	DIFFERENTIAL
接口集成电路类型：	LINE RECEIVER	接口标准：	EIA-644; TIA-644; IEEE 1596.3
JESD-30 代码：	R-CDFP-F16	功能数量：	4
端子数量：	16	最高工作温度：	125 °C
最低工作温度：	-55 °C	封装主体材料：	CERAMIC, METAL-SEALED COFIRED
封装代码：	DFP	封装形状：	RECTANGULAR
封装形式：	FLATPACK	认证状态：	Not Qualified
最大接收延迟：	8 ns	接收器位数：	4
筛选级别：	MIL-PRF-38535 Class V	座面最大高度：	2.921 mm
最大供电电压：	5.5 V	最小供电电压：	4.5 V
标称供电电压：	5 V	表面贴装：	YES
技术：	CMOS	温度等级：	MILITARY
端子形式：	FLAT	端子节距：	1.27 mm
端子位置：	DUAL	总剂量：	100k Rad(Si) V
宽度：	6.731 mm	Base Number Matches：	1

5962R9583403QXA 数据手册

Standard Products

UT54LVDS032 Quad Receiver

Data Sheet

May 22, 2003

FEATURES

INTRODUCTION

The UT54LVDS032 Quad Receiver is a quad CMOS

differential line receiver designed for applications requiring

ultra low power dissipation and high data rates. The device

is designed to support data rates in excess of 155.5 Mbps

(77.7 MHz) utilizing Low Voltage Differential Signaling

(LVDS) technology.

>155.5 Mbps (77.7 MHz) switching rates

+340mV differential signaling

5 V power supply

TTL compatible outputs

Ultra low power CMOS technology

8.0ns maximum propagation delay

3.0ns maximum differential skew

The UT54LVDS032 accepts low voltage (340mV)

differential input signals and translates them to 5V TTL

output levels. The receiver supports a three-state function

that may be used to multiplex outputs. The receiver also

supports OPEN, shorted and terminated (100W) input fail-

safe. Receiver output will be HIGH for all fail-safe

conditions.

Radiation-hardened design; total dose irradiation testing to

MIL-STD-883 Method 1019

- Total-dose: 300 krad(Si)and 1Mrad(Si)

- Latchup immune (LET > 111 M eV-cm²/mg)

The UT54LVDS032 and companion quad line driver

UT54LVDS031 provides new alternatives to high power

pseudo-ECL devices for high speed point-to-point interface

applications.

Packaging options:

- 16-lead flatpack (dual in-line)

Standard Microcircuit Drawing5962-95834

- QML Q and V compliant part

Compatible with IEEE 1596.3SCI LVDS

Compatible with ANSI/TIA/EIA 644-1996 LVDS Standard

R_IN1+

R_IN1-

R_OUT1

R_IN2+

R_IN2-

R_OUT2

R_IN3+

R_IN3-

R_OUT3

R_IN4+

R_IN4-

R_OUT4

Figure 1. UT54LVDS032 Quad Receiver Block Diagram

12 3 4 5 6 7...11

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