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SMP18FP PDF预览

SMP18FP

更新时间: 2024-01-27 15:59:06
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
8页 271K
描述
Octal Sample-and-Hold with Multiplexed Input

SMP18FP 技术参数

是否无铅: 含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:SOIC
包装说明:SOP,针数:16
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.31.00.01风险等级:5.07
标称采集时间:3.5 µs放大器类型:SAMPLE AND HOLD CIRCUIT
最大模拟输入电压:3 V最小模拟输入电压:-3 V
最大下降率:0.04 V/sJESD-30 代码:R-PDSO-G16
JESD-609代码:e3长度:9.9 mm
湿度敏感等级:1负供电电压上限:-8.5 V
标称负供电电压 (Vsup):-5 V功能数量:8
端子数量:16最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):240
认证状态:Not Qualified采样并保持/跟踪并保持:SAMPLE
座面最大高度:1.75 mm子类别:Sample and Hold Circuit
最大压摆率:9.5 mA供电电压上限:8.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:3.9 mm
Base Number Matches:1

SMP18FP 数据手册

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Octal Sample-and-Hold  
with Multiplexed Input  
a
SMP18  
FEATURES  
FUNCTIONAL BLOCK DIAGRAM  
High Speed Version of SMP08  
Internal Hold Capacitors  
Low Droop Rate  
TTL/CMOS Compatible Logic Inputs  
Single or Dual Supply Operation  
Break-Before-Make Channel Addressing  
Compatible With CD4051 Pinout  
Low Cost  
(LSB)  
A
(MSB)  
C
INPUT  
3
B
INH  
6
11  
10  
9
8
DGND  
1 OF 8 DECODER  
16  
13  
V
DD  
SW  
CH OUT  
0
APPLICATIONS  
14  
SW  
CH OUT  
1
Multiple Path Timing Deskew for A.T.E.  
Memory Programmers  
SW  
15 CH OUT  
2
Mass Flow/Process Control Systems  
Multichannel Data Acquisition Systems  
Robotics and Control Systems  
Medical and Analytical Instrumentation  
Event Analysis  
SW  
12 CH OUT  
3
CH OUT  
4
SW  
1
5
2
4
Stage Lighting Control  
CH OUT  
5
SW  
GENERAL DESCRIPTION  
CH OUT  
6
SW  
The SMP18 is a monolithic octal sample-and-hold; it has eight  
internal buffer amplifiers, input multiplexer, and internal hold  
capacitors. It is manufactured in an advanced oxide isolated  
CMOS technology to obtain high accuracy, low droop rate, and  
fast acquisition time. The SMP18 has a typical linearity error of  
only 0.01% and can accurately acquire a 10-bit input signal to  
±1/2 LSB in less than 2.5 microseconds. The SMP18’s output  
swing includes the negative supply in both single and dual sup-  
ply operation.  
SW  
CH OUT  
7
HOLD CAPS  
(INTERNAL)  
V
7
SS  
SMP18  
The SMP18 was specifically designed for systems that use a  
calibration cycle to adjust a multiple of system parameters. The  
low cost and high level of integration make the SMP18 ideal for  
calibration requirements that have previously required an ASIC,  
or high cost multiple D/A converters.  
The SMP18 offers significant cost and size reduction over  
discrete designs. It is available in a 16-pin plastic DIP, a  
narrow body SO-16 surface-mount SOIC package or the thin  
TSSOP-16 package. The SMP18 is a higher speed direct  
replacement for the SMP08.  
The SMP18 is also ideally suited for a wide variety of sample-  
and-hold applications including amplifier offset or VCA gain ad-  
justments. One or more SMP18s can be used with single or  
multiple DACs to provide multiple set points within a system.  
REV. C  
Information furnished by Analog Devices is believed to be accurate and  
reliable. However, no responsibility is assumed by Analog Devices for its  
use, nor for any infringements of patents or other rights of third parties  
which may result from its use. No license is granted by implication or  
otherwise under any patent or patent rights of Analog Devices.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 617/329-4700  
Fax: 617/326-8703  
World Wide Web Site: http://www.analog.com  
© Analog Devices, Inc., 1996  

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