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SMP08FSZ-REEL PDF预览

SMP08FSZ-REEL

更新时间: 2024-01-25 02:57:32
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
8页 265K
描述
Low Droop Rate Octal Sample-and-Hold with Multiplexed Input

SMP08FSZ-REEL 技术参数

生命周期:ObsoleteReach Compliance Code:unknown
风险等级:5.63放大器类型:SAMPLE AND HOLD CIRCUIT
JESD-30 代码:R-PDSO-G16端子数量:16
封装主体材料:PLASTIC/EPOXY封装形状:RECTANGULAR
封装形式:SMALL OUTLINE认证状态:Not Qualified
子类别:Sample and Hold Circuit表面贴装:YES
端子形式:GULL WING端子位置:DUAL
Base Number Matches:1

SMP08FSZ-REEL 数据手册

 浏览型号SMP08FSZ-REEL的Datasheet PDF文件第2页浏览型号SMP08FSZ-REEL的Datasheet PDF文件第3页浏览型号SMP08FSZ-REEL的Datasheet PDF文件第4页浏览型号SMP08FSZ-REEL的Datasheet PDF文件第5页浏览型号SMP08FSZ-REEL的Datasheet PDF文件第6页浏览型号SMP08FSZ-REEL的Datasheet PDF文件第7页 
Octal Sample-and-Hold  
with Multiplexed Input  
a
SMP08*  
FUNCTIONAL BLOCK DIAGRAM  
FEATURES  
Internal Hold Capacitors  
Low Droop Rate  
(LSB)  
A
(MSB)  
C
INPUT  
3
B
INH  
6
TTL/CMOS Compatible Logic Inputs  
Single or Dual Supply Operation  
Break-Before-Make Channel Addressing  
Compatible With CD4051 Pinout  
Low Cost  
11  
10  
9
8
DGND  
1 OF 8 DECODER  
16  
13  
V
DD  
SW  
CH OUT  
0
APPLICATIONS  
Multiple Path Timing Deskew for ATE  
Memory Programmers  
Mass Flow/Process Control Systems  
Multichannel Data Acquisition Systems  
Robotics and Control Systems  
Medical and Analytical Instrumentation  
Event Analysis  
14  
SW  
CH OUT  
1
SW  
15 CH OUT  
2
SW  
12 CH OUT  
3
CH OUT  
4
SW  
1
5
2
4
Stage Lighting Control  
CH OUT  
5
SW  
CH OUT  
6
SW  
GENERAL DESCRIPTION  
SW  
CH OUT  
7
The SMP08 is a monolithic octal sample-and-hold; it has eight  
internal buffer amplifiers, input multiplexer, and internal hold  
capacitors. It is manufactured in an advanced oxide isolated  
CMOS technology to obtain high accuracy, low droop rate, and  
fast acquisition time. The SMP08 has a typical linearity error of  
only 0.01% and can accurately acquire a 10-bit input signal to  
±1/2 LSB in less than 7 microseconds. The SMP08’s output  
swing includes the negative supply in both single and dual sup-  
ply operation.  
HOLD CAPS  
(INTERNAL)  
V
7
SS  
SMP08  
The SMP08 is also ideally suited for a wide variety of sample-  
and-hold applications including amplifier offset or VCA gain  
adjustments. One or more SMP08s can be used with single or  
multiple DACs to provide multiple set points within a system.  
The SMP08 was specifically designed for systems that use a  
calibration cycle to adjust a multiple of system parameters. The  
low cost and high level of integration make the SMP08 ideal for  
calibration requirements that have previously required an  
ASIC, or high cost multiple D/A converters.  
The SMP08 offers significant cost and size reduction over dis-  
crete designs. It is available in a 16-pin plastic DIP, or surface-  
mount SOIC package.  
*Protected by U.S. Patent No. 4,739,281.  
REV. D  
Information furnished by Analog Devices is believed to be accurate and  
reliable. However, no responsibility is assumed by Analog Devices for its  
use, nor for any infringements of patents or other rights of third parties  
which may result from its use. No license is granted by implication or  
otherwise under any patent or patent rights of Analog Devices.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 617/329-4700  
Fax: 617/326-8703  
World Wide Web Site: http://www.analog.com  
© Analog Devices, Inc., 1996  

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