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ADuM3221BRZ PDF预览

ADuM3221BRZ

更新时间: 2024-02-23 07:13:50
品牌 Logo 应用领域
亚德诺 - ADI 驱动器MOSFET驱动器栅极驱动程序和接口接口集成电路光电二极管双极性晶体管栅极驱动PC
页数 文件大小 规格书
16页 614K
描述
Isolated, 4 A Dual-Channel Gate Driver

ADuM3221BRZ 技术参数

是否无铅: 含铅是否Rohs认证: 符合
生命周期:Active包装说明:SOP, SOP8,.25
针数:8Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.55Is Samacsys:N
内置保护:TRANSIENT; OVER VOLTAGE; THERMAL; UNDER VOLTAGE高边驱动器:NO
接口集成电路类型:BUFFER OR INVERTER BASED PERIPHERAL DRIVERJESD-30 代码:R-PDSO-G8
JESD-609代码:e3长度:4.9 mm
湿度敏感等级:3功能数量:2
端子数量:8最高工作温度:125 °C
最低工作温度:-40 °C最大输出电流:0.23 A
标称输出峰值电流:4 A封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP8,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):260筛选级别:AEC-Q100
座面最大高度:1.75 mm最大压摆率:17 mA
最大供电电压:5.5 V最小供电电压:3 V
标称供电电压:3.3 V电源电压1-最大:18 V
电源电压1-分钟:4.5 V电源电压1-Nom:10 V
表面贴装:YES技术:CMOS
温度等级:AUTOMOTIVE端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
断开时间:0.72 µs接通时间:0.72 µs
宽度:3.9 mmBase Number Matches:1

ADuM3221BRZ 数据手册

 浏览型号ADuM3221BRZ的Datasheet PDF文件第2页浏览型号ADuM3221BRZ的Datasheet PDF文件第3页浏览型号ADuM3221BRZ的Datasheet PDF文件第4页浏览型号ADuM3221BRZ的Datasheet PDF文件第5页浏览型号ADuM3221BRZ的Datasheet PDF文件第6页浏览型号ADuM3221BRZ的Datasheet PDF文件第7页 
Isolated, 4 A Dual-Channel Gate Driver  
Data Sheet  
ADuM3220/ADuM3221  
FEATURES  
GENERAL DESCRIPTION  
The ADuM3220/ADuM32211 are isolated, 4 A dual-channel gate  
4 A peak output current  
Precise timing characteristics  
drivers based on the Analog Devices, Inc., iCoupler® technology.  
60 ns maximum isolator and driver propagation delay  
5 ns maximum channel-to-channel matching  
High junction temperature operation: 125°C  
3.3 V to 5 V input logic  
Combining high speed CMOS and monolithic transformer technol-  
ogy, these isolation components provide outstanding performance  
characteristics superior to the alternatives, such as the combination  
of pulse transformers and gate drivers.  
4.5 V to 18 V output drive  
The ADuM3220/ADuM3221 provide digital isolation in two  
independent isolation channels. They have a maximum propagation  
delay of 60 ns and 5 ns channel-to-channel matching. In comparison  
to gate drivers that employ high voltage level translation method-  
ologies, the ADuM3220/ADuM3221 offer the benefit of true,  
galvanic isolation between the input and each output, enabling  
voltage translation across the isolation barrier. The ADuM3220  
has shoot-through protection logic, which prevents both outputs  
from being on at the same time, whereas the ADuM3221 allows  
both outputs to be on at the same time. Both parts offer a default  
output low characteristic as required for gate drive applications.  
UVLO at 2.5 V VDD1  
ADuM3220A/ADuM3221A UVLO at 4.1 V VDD2  
ADuM3220B/ADuM3221B UVLO at 7.0 V VDD2  
Thermal shutdown protection at >150°C  
Output shoot-through logic protection on the ADuM3220  
Default low output  
High frequency operation: dc to 1 MHz  
CMOS input logic levels  
High common-mode transient immunity: >25 kV/μs  
Enhanced system-level ESD performance per IEC 61000-4-x  
Safety and regulatory approvals  
The ADuM3220/ADuM3221 operate with an input supply voltage  
ranging from 3.0 V to 5.5 V, providing compatibility with lower  
voltage systems. The outputs of the ADuM3220A/ADuM3221A  
can be operated at supply voltages from 4.5 V to 18 V. The outputs  
of the ADuM3220B/ADuM3221B can be operated at supply  
voltages from 7.6 V to 18 V.  
UL recognition  
2500 V rms for 1 minute per UL 1577  
CSA Component Acceptance Notice #5A  
VDE certificate of conformity  
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12  
V
IORM = 560 V peak  
Small footprint and low profile  
Narrow body, RoHS-compliant, 8-lead SOIC  
5 mm × 6 mm × 1.6 mm  
The junction temperature of the ADuM3220/ADuM3221 is  
specified from −40°C to +125°C.  
Qualified for automotive applications  
APPLICATIONS  
Isolated synchronous dc-to-dc converters  
MOSFET/IGBT gate drivers  
FUNCTIONAL BLOCK DIAGRAMS  
ADuM3220  
ADuM3221  
1
2
8
7
1
2
8
7
V
V
V
V
V
V
DD1  
DD2  
OA  
DD1  
DD2  
OA  
DECODE  
AND  
DECODE  
AND  
ENCODE  
ENCODE  
ENCODE  
V
V
IA  
IA  
LEVEL  
SHIFT  
LEVEL  
SHIFT  
DECODE  
AND  
LEVEL  
SHIFT  
DECODE  
AND  
LEVEL  
SHIFT  
3
4
ENCODE  
6
5
3
4
6
5
V
V
V
V
IB  
OB  
IB  
OB  
GND  
GND  
GND  
GND  
2
1
2
1
Figure 1.  
Figure 2.  
1 Protected by U.S. Patents 5,952,849; 6,873,065; 7,075,239.  
Rev. C Document Feedback  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rights of third parties that may result from its use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks and registeredtrademarks arethe property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700 ©2010–2012 Analog Devices, Inc. All rights reserved.  
Technical Support  
www.analog.com  
 
 
 
 

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