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ADSP-2185NKCA-320 PDF预览

ADSP-2185NKCA-320

更新时间: 2024-02-24 13:15:11
品牌 Logo 应用领域
亚德诺 - ADI 微控制器和处理器外围集成电路数字信号处理器电脑时钟
页数 文件大小 规格书
48页 1466K
描述
DSP Microcomputer

ADSP-2185NKCA-320 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Active零件包装代码:BGA
包装说明:LFBGA,针数:144
Reach Compliance Code:unknown风险等级:5.65
地址总线宽度:14桶式移位器:YES
边界扫描:NO最大时钟频率:40 MHz
外部数据总线宽度:24格式:FIXED POINT
内部总线架构:MULTIPLEJESD-30 代码:S-PBGA-B144
JESD-609代码:e0长度:10 mm
低功率模式:YES湿度敏感等级:3
端子数量:144最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:LFBGA封装形状:SQUARE
封装形式:GRID ARRAY, LOW PROFILE, FINE PITCH峰值回流温度(摄氏度):240
认证状态:COMMERCIAL座面最大高度:1.4 mm
最大供电电压:1.89 V最小供电电压:1.71 V
标称供电电压:1.8 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:TIN LEAD SILVER端子形式:BALL
端子节距:0.8 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:30宽度:10 mm
uPs/uCs/外围集成电路类型:DIGITAL SIGNAL PROCESSOR, OTHERBase Number Matches:1

ADSP-2185NKCA-320 数据手册

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a
DSP Microcomputer  
ADSP-218xN Series  
PERFORMANCE FEATURES  
12.5 ns Instruction Cycle Time @1.8 V (Internal), 80 MIPS  
Sustained Performance  
Programmable 16-Bit Interval Timer with Prescaler  
100-Lead LQFP and 144-Ball Mini-BGA  
Single-Cycle Instruction Execution  
Single-Cycle Context Switch  
3-Bus Architecture Allows Dual Operand Fetches in  
Every Instruction Cycle  
SYSTEM INTERFACE FEATURES  
Flexible I/O Allows 1.8 V, 2.5 V or 3.3 V Operation  
All Inputs Tolerate up to 3.6 V Regardless of Mode  
16-Bit Internal DMA Port for High-Speed Access to On-  
Chip Memory (Mode Selectable)  
Multifunction Instructions  
Power-Down Mode Featuring Low CMOS Standby  
Power Dissipation with 200 CLKIN Cycle Recovery  
from Power-Down Condition  
4M-Byte Memory Interface for Storage of Data Tables  
and Program Overlays (Mode Selectable)  
8-Bit DMA to Byte Memory for Transparent Program and  
Data Memory Transfers (Mode Selectable)  
Programmable Memory Strobe and Separate I/O  
Memory Space Permits “Glueless” System Design  
Programmable Wait State Generation  
Two Double-Buffered Serial Ports with Companding  
Hardware and Automatic Data Buffering  
Automatic Booting of On-Chip Program Memory from  
Byte-Wide External Memory, e.g., EPROM, or through  
Internal DMA Port  
Low Power Dissipation in Idle Mode  
INTEGRATION FEATURES  
ADSP-2100 Family Code Compatible (Easy to Use  
Algebraic Syntax), with Instruction Set Extensions  
Up to 256K Bytes of On-Chip RAM, Configured as  
Up to 48K Words Program Memory RAM  
Up to 56K Words Data Memory RAM  
Dual-Purpose Program Memory for Both Instruction and  
Data Storage  
Six External Interrupts  
Independent ALU, Multiplier/Accumulator, and Barrel  
Shifter Computational Units  
13 Programmable Flag Pins Provide Flexible System  
Signaling  
Two Independent Data Address Generators  
Powerful Program Sequencer Provides Zero Overhead  
Looping Conditional Instruction Execution  
UART Emulation through Software SPORT  
Reconfiguration  
ICE-Port™ Emulator Interface Supports Debugging in  
Final Systems  
FUNCTIONAL BLOCK DIAGRAM  
POWER-DOWN  
CONTROL  
FULL MEMORY MODE  
MEMORY  
PROGRAMMABLE  
PROGRAM  
EXTERNAL  
ADDRESS  
BUS  
DATA  
MEMORY  
UP TO  
DATA ADDRESS  
GENERATORS  
I/O  
MEMORY  
AND  
FLAGS  
PROGRAM  
SEQUENCER  
UP TO  
DAG1 DAG2  
48K 24-BIT  
56K 16-BIT  
EXTERNAL  
DATA  
BUS  
PROGRAM MEMORY ADDRESS  
BYTE DMA  
CONTROLLER  
DATA MEMORY ADDRESS  
PROGRAM MEMORY DATA  
DATA MEMORY DATA  
OR  
EXTERNAL  
DATA  
BUS  
ARITHMETIC UNITS  
MAC SHIFTER  
SERIAL PORTS  
TIMER  
INTERNAL  
DMA  
PORT  
ALU  
SPORT0  
SPORT1  
ADSP-2100 BASE  
ARCHITECTURE  
HOST MODE  
ICE-Port is a trademark of Analog Devices, Inc.  
REV. 0  
Information furnished by Analog Devices is believed to be accurate and reli-  
able. However, no responsibility is assumed by Analog Devices for its use,  
nor for any infringements of patents or other rights of third parties that may One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106, U.S.A.  
result from its use. No license is granted by implication or otherwise under Tel:781/329-4700  
any patent or patent rights of Analog Devices. Fax:781/326-8703  
http://www.analog.com  
© Analog Devices, Inc., 2001  

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