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ADSP-2183KST-133 PDF预览

ADSP-2183KST-133

更新时间: 2024-01-26 07:58:29
品牌 Logo 应用领域
亚德诺 - ADI 外围集成电路电脑时钟
页数 文件大小 规格书
31页 251K
描述
DSP Microcomputer

ADSP-2183KST-133 技术参数

是否无铅:含铅是否Rohs认证:不符合
生命周期:Active零件包装代码:QFP
包装说明:LFQFP,针数:128
Reach Compliance Code:unknown风险等级:5.72
Is Samacsys:N地址总线宽度:14
桶式移位器:YES边界扫描:NO
最大时钟频率:16.67 MHz外部数据总线宽度:24
格式:FIXED POINT内部总线架构:MULTIPLE
JESD-30 代码:R-PQFP-G128JESD-609代码:e0
长度:20 mm低功率模式:YES
湿度敏感等级:3端子数量:128
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:LFQFP
封装形状:RECTANGULAR封装形式:FLATPACK, LOW PROFILE, FINE PITCH
峰值回流温度(摄氏度):240认证状态:COMMERCIAL
座面最大高度:1.6 mm最大供电电压:3.6 V
最小供电电压:3 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:TIN LEAD
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:14 mmuPs/uCs/外围集成电路类型:DIGITAL SIGNAL PROCESSOR, OTHER
Base Number Matches:1

ADSP-2183KST-133 数据手册

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a
DSP Microcomputer  
ADSP-2183  
FUNCTIONAL BLOCK DIAGRAM  
FEATURES  
PERFORMANCE  
19 ns Instruction Cycle Time from 26.32 MHz Crystal  
@ 3.3 Volts  
52 MIPS Sustained Performance  
Single-Cycle Instruction Execution  
Single-Cycle Context Switch  
3-Bus Architecture Allows Dual Operand Fetches in  
Every Instruction Cycle  
POWERDOWN  
PROGRAMMABLE  
CONTROL  
I/O  
FLAGS  
MEMORY  
DATA ADDRESS  
GENERATORS  
PROGRAM  
SEQUENCER  
PROGRAM  
MEMORY  
DATA  
MEMORY  
BYTE DMA  
CONTROLLER  
DAG 1 DAG 2  
EXTERNAL  
ADDRESS  
BUS  
PROGRAM MEMORY ADDRESS  
DATA MEMORY ADDRESS  
Multifunction Instructions  
PROGRAM MEMORY DATA  
DATA MEMORY DATA  
Power-Down Mode Featuring Low CMOS Standby  
Power Dissipation with 300 Cycle Recovery from  
Power-Down Condition  
EXTERNAL  
DATA  
BUS  
ARITHMETIC UNITS  
SERIAL PORTS  
SPORT 0 SPORT 1  
INTERNAL  
DMA  
PORT  
TIMER  
Low Power Dissipation in Idle Mode  
ALU MAC SHIFTER  
DMA  
BUS  
INTEGRATION  
ADSP-2100 Family Code Compatible, with Instruction  
Set Extensions  
ADSP-2100 BASE  
ARCHITECTURE  
80K Bytes of On-Chip RAM, Configured as  
16K Words On-Chip Program Memory RAM  
16K Words On-Chip Data Memory RAM  
Dual Purpose Program Memory for Both Instruction  
and Data Storage  
Independent ALU, Multiplier/Accumulator, and Barrel  
Shifter Computational Units  
Two Independent Data Address Generators  
Powerful Program Sequencer Provides  
Zero Overhead Looping  
Conditional Instruction Execution  
Programmable 16-Bit Interval Timer with Prescaler  
128-Lead LQFP, 144-Ball Mini-BGA  
GENERAL DESCRIPTION  
The ADSP-2183 is a single-chip microcomputer optimized for  
digital signal processing (DSP) and other high speed numeric  
processing applications.  
The ADSP-2183 combines the ADSP-2100 family base architec-  
ture (three computational units, data address generators and  
a program sequencer) with two serial ports, a 16-bit internal  
DMA port, a byte DMA port, a programmable timer, Flag I/O,  
extensive interrupt capabilities, and on-chip program and  
data memory.  
The ADSP-2183 integrates 80K bytes of on-chip memory con-  
figured as 16K words (24-bit) of program RAM, and 16K words  
(16-bit) of data RAM. Power-down circuitry is also provided to  
meet the low power needs of battery operated portable equipment.  
The ADSP-2183 is available in 128-lead LQFP, and 144-Ball  
Mini-BGA packages.  
SYSTEM INTERFACE  
16-Bit Internal DMA Port for High Speed Access to  
On-Chip Memory  
4 MByte Memory Interface for Storage of Data Tables  
and Program Overlays  
In addition, the ADSP-2183 supports new instructions, which  
include bit manipulations—bit set, bit clear, bit toggle, bit test—  
new ALU constants, new multiplication instruction (x squared),  
biased rounding, result free ALU operations, I/O memory trans-  
fers and global interrupt masking, for increased flexibility.  
8-Bit DMA to Byte Memory for Transparent  
Program and Data Memory Transfers  
I/O Memory Interface with 2048 Locations Supports  
Parallel Peripherals  
Programmable Memory Strobe and Separate I/O  
Memory Space Permits “Glueless” System Design  
Programmable Wait State Generation  
Two Double-Buffered Serial Ports with Companding  
Hardware and Automatic Data Buffering  
Automatic Booting of On-Chip Program Memory from  
Byte-Wide External Memory, e.g., EPROM, or  
Through Internal DMA Port  
Six External Interrupts  
13 Programmable Flag Pins Provide Flexible System  
Signaling  
ICE-Port™ Emulator Interface Supports Debugging  
in Final Systems  
Fabricated in a high speed, double metal, low power, CMOS  
process, the ADSP-2183 operates with a 19 ns instruction cycle  
time. Every instruction can execute in a single processor cycle.  
The ADSP-2183’s flexible architecture and comprehensive  
instruction set allow the processor to perform multiple opera-  
tions in parallel. In one processor cycle the ADSP-2183 can:  
• Generate the next program address  
• Fetch the next instruction  
• Perform one or two data moves  
• Update one or two data address pointers  
• Perform a computational operation  
ICE-Port is a trademark of Analog Devices, Inc.  
REV. C  
Information furnished by Analog Devices is believed to be accurate and  
reliable. However, no responsibility is assumed by Analog Devices for its  
use, nor for any infringements of patents or other rights of third parties  
which may result from its use. No license is granted by implication or  
otherwise under any patent or patent rights of Analog Devices.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781/329-4700  
Fax: 781/326-8703  
World Wide Web Site: http://www.analog.com  
© Analog Devices, Inc., 2000  

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