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ADSP-2181KST-115 PDF预览

ADSP-2181KST-115

更新时间: 2024-01-14 10:15:20
品牌 Logo 应用领域
亚德诺 - ADI 微控制器和处理器外围集成电路数字信号处理器装置电脑时钟
页数 文件大小 规格书
32页 293K
描述
DSP Microcomputer

ADSP-2181KST-115 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:QFP包装说明:TQFP-128
针数:128Reach Compliance Code:not_compliant
ECCN代码:3A991.A.2HTS代码:8542.31.00.01
风险等级:5.83其他特性:33 MIPS SUSTAINED; SINGLE CYCLE INSTRUCTION EXECUTION
地址总线宽度:14桶式移位器:YES
位大小:16边界扫描:NO
最大时钟频率:14.4 MHz外部数据总线宽度:24
格式:FIXED POINT集成缓存:NO
内部总线架构:MULTIPLEJESD-30 代码:R-PQFP-G128
JESD-609代码:e0长度:20 mm
低功率模式:YES湿度敏感等级:3
DMA 通道数量:2外部中断装置数量:4
串行 I/O 数:2端子数量:128
计时器数量:1片上数据RAM宽度:16
片上程序ROM宽度:最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:LFQFP封装等效代码:QFP128,.63X.87,20
封装形状:RECTANGULAR封装形式:FLATPACK, LOW PROFILE, FINE PITCH
峰值回流温度(摄氏度):240电源:5 V
认证状态:Not QualifiedRAM(字数):8192
座面最大高度:1.6 mm子类别:Digital Signal Processors
最大压摆率:100 mA最大供电电压:5.5 V
最小供电电压:4.5 V标称供电电压:5 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:14 mmuPs/uCs/外围集成电路类型:DIGITAL SIGNAL PROCESSOR, OTHER
Base Number Matches:1

ADSP-2181KST-115 数据手册

 浏览型号ADSP-2181KST-115的Datasheet PDF文件第2页浏览型号ADSP-2181KST-115的Datasheet PDF文件第3页浏览型号ADSP-2181KST-115的Datasheet PDF文件第4页浏览型号ADSP-2181KST-115的Datasheet PDF文件第5页浏览型号ADSP-2181KST-115的Datasheet PDF文件第6页浏览型号ADSP-2181KST-115的Datasheet PDF文件第7页 
a
DSP Microcomputer  
ADSP-2181  
FUNCTIO NAL BLO CK D IAGRAM  
FEATURES  
PERFORMANCE  
25 ns Instruction Cycle Tim e from 20 MHz Crystal  
@ 5.0 Volts  
40 MIPS Sustained Perform ance  
Single-Cycle Instruction Execution  
Single-Cycle Context Sw itch  
PROGRAMMABLE  
I/O  
POWER-DOWN  
CONTROL  
FLAGS  
MEMORY  
DATA ADDRESS  
GENERATORS  
PROGRAM  
SEQUENCER  
DATA  
MEMORY  
PROGRAM  
MEMORY  
BYTE DMA  
CONTROLLER  
DAG 1 DAG 2  
EXTERNAL  
ADDRESS  
BUS  
3-Bus Architecture Allow s Dual Operand Fetches in  
Every Instruction Cycle  
Multifunction Instructions  
Pow er-Dow n Mode Featuring Low CMOS Standby  
Pow er Dissipation w ith 100 Cycle Recovery from  
Pow er-Dow n Condition  
PROGRAM MEMORY ADDRESS  
DATA MEMORY ADDRESS  
EXTERNAL  
DATA BUS  
PROGRAM MEMORY DATA  
DATA MEMORY DATA  
DMA BUS  
INTERNAL  
DMA  
PORT  
SERIAL PORTS  
SPORT 0 SPORT 1  
ARITHMETIC UNITS  
ALU MAC SHIFTER  
TIMER  
Low Pow er Dissipation in Idle Mode  
INTEGRATION  
ADSP-2100 Fam ily Code Com patible, w ith Instruction  
Set Extensions  
ADSP-2100 BASE  
ARCHITECTURE  
80K Bytes of On-Chip RAM, Configured as  
16K Words On-Chip Program Mem ory RAM  
16K Words On-Chip Data Mem ory RAM  
Dual Purpose Program Mem ory for Both Instruction  
and Data Storage  
GENERAL D ESCRIP TIO N  
T he ADSP-2181 is a single-chip microcomputer optimized for  
digital signal processing (DSP) and other high speed numeric  
processing applications.  
Independent ALU, Multiplier/ Accum ulator, and Barrel  
Shifter Com putational Units  
Tw o Independent Data Address Generators  
Pow erful Program Sequencer Provides  
Zero Overhead Looping  
Conditional Instruction Execution  
Program m able 16-Bit Interval Tim er w ith Prescaler  
128-Lead TQFP/ 128-Lead PQFP  
T he ADSP-2181 combines the ADSP-2100 family base archi-  
tecture (three computational units, data address generators and  
a program sequencer) with two serial ports, a 16-bit internal  
DMA port, a byte DMA port, a programmable timer, Flag I/O,  
extensive interrupt capabilities, and on-chip program and data  
memory.  
T he ADSP-2181 integrates 80K bytes of on-chip memory con-  
figured as 16K words (24-bit) of program RAM, and 16K words  
(16-bit) of data RAM. Power-down circuitry is also provided to  
meet the low power needs of battery operated portable equip-  
ment. T he ADSP-2181 is available in 128-lead T QFP and 128-  
lead PQFP packages.  
SYSTEM INTERFACE  
16-Bit Internal DMA Port for High Speed Access to  
On-Chip Mem ory  
4 MByte Mem ory Interface for Storage of Data Tables  
and Program Overlays  
8-Bit DMA to Byte Mem ory for Transparent  
Program and Data Mem ory Transfers  
I/ O Mem ory Interface w ith 2048 Locations Supports  
Parallel Peripherals  
Program m able Mem ory Strobe and Separate I/ O Mem ory  
Space Perm its “Glueless” System Design  
Program m able Wait State Generation  
Tw o Double-Buffered Serial Ports w ith Com panding  
Hardw are and Autom atic Data Buffering  
Autom atic Booting of On-Chip Program Mem ory from  
Byte-Wide External Mem ory, e.g., EPROM, or  
Through Internal DMA Port  
In addition, the ADSP-2181 supports new instructions, which  
include bit manipulations—bit set, bit clear, bit toggle, bit test—  
new ALU constants, new multiplication instruction (x squared),  
biased rounding, result free ALU operations, I/O memory trans-  
fers and global interrupt masking for increased flexibility.  
Fabricated in a high speed, double metal, low power, CMOS  
process, the ADSP-2181 operates with a 25 ns instruction cycle  
time. Every instruction can execute in a single processor cycle.  
T he ADSP-2181s flexible architecture and comprehensive  
instruction set allow the processor to perform multiple opera-  
tions in parallel. In one processor cycle the ADSP-2181 can:  
Six External Interrupts  
13 Program m able Flag Pins Provide Flexible System  
Signaling  
Generate the next program address  
Fetch the next instruction  
ICE-Port™ Em ulator Interface Supports Debugging  
in Final System s  
ICE -P or t is a tr adem ar k of Analog D evices, Inc.  
• Perform one or two data moves  
Update one or two data address pointers  
• Perform a computational operation  
REV. D  
Inform ation furnished by Analog Devices is believed to be accurate and  
reliable. However, no responsibility is assum ed by Analog Devices for its  
use, nor for any infringem ents of patents or other rights of third parties  
which m ay result from its use. No license is granted by im plication or  
otherwise under any patent or patent rights of Analog Devices.  
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.  
Tel: 781/ 329-4700  
Fax: 781/ 326-8703  
World Wide Web Site: http:/ / w w w .analog.com  
© Analog Devices, Inc., 1998  

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