a
DSP Microcomputer
ADSP-2171/ADSP-2172/ADSP-2173
FUNCTIO NAL BLO CK D IAGRAM
FEATURES
30 ns Instruction Cycle Tim e (33 MIPS) from
16.67 MHz Crystal at 5.0 V
50 ns Instruction Cycle Tim e (20 MIPS) from 10 MHz
Crystal at 3.3 V
POWERDOWN
PROGRAM
MEMORY
CONTROL
ROM
LOGIC
8K x 24
DATA
ADDRESS
PROGRAM
SEQUENCER
PROGRAM
RAM
2K x 24
DATA
MEMORY
2K x 16
GENERATORS
FLAGS
DAG 1
DAG 2
ADSP-2100 Fam ily Code & Function Com patible w ith
New Instruction Set Enhancem ents for Bit Manipula-
tion Instructions, Multiplication Instructions, Biased
Rounding, and Global Interrupt Masking
Bus Grant Hang Logic
EXTERNAL
ADDRESS
BUS
PROGRAM MEMORY ADDRESS
DATA MEMORY ADDRESS
PROGRAM MEMORY DATA
2K Words of On-Chip Program Mem ory RAM
2K Words of On-Chip Data Mem ory RAM
8K Words of On-Chip Program Mem ory ROM
(ADSP-2172)
8- or 16-Bit Parallel Host Interface Port
300 m W Typical Pow er Dissipation at 5.0 V at 30 ns
70 m W Typical Pow er Dissipation at 3.3 V at 50 ns
Pow erdow n Mode Featuring Less than 0.55 m W (ADSP-
2171/ ADSP-2172) or 0.36 m W (ADSP-2173) CMOS
Standby Pow er Dissipation w ith 100 Cycle Recovery
from Pow erdow n
DATA MEMORY DATA
EXTERNAL
DATA
BUS
ARITHMETIC UNITS
MAC
TIMER
SERIAL PORTS
SPORT 0
HOST
INTERFACE
PORT
SHIFTER
ALU
SPORT 1
ADSP-2100 BASE
ARCHITECTURE
T he ADSP-217x combines the ADSP-2100 base architecture
(three computational units, data address generators, and a pro-
gram sequencer) with two serial ports, a host interface port, a
programmable timer, extensive interrupt capabilities, and on-
chip program and data memory.
Dual Purpose Program Mem ory for Both Instruction
and Data Storage
In addition, the ADSP-217x supports new instructions, which
include bit manipulations–bit set, bit clear, bit toggle, bit test–
new ALU constants, new multiplication instruction (x squared),
biased rounding, and global interrupt masking, for increased
flexibility. T he ADSP-217x also has a Bus Grant Hang Logic
(BGH) feature.
Independent ALU, Multiplier/ Accum ulator, and Barrel
Shifter Com putational Units
Tw o Independent Data Address Generators
Pow erful Program Sequencer Provides
Zero Overhead Looping
Conditional Instruction Execution
Tw o Double-Buffered Serial Ports w ith Com panding
Hardw are and Autom atic Data Buffering
Program m able 16-Bit Interval Tim er w ith Prescaler
Program m able Wait State Generation
Autom atic Booting of Internal Program Mem ory from
Byte-Wide External Mem ory, e.g., EPROM, or
Through Host Interface Port
Stand-Alone ROM Execution (Optional)
Single-Cycle Instruction Execution
Single-Cycle Context Sw itch
T he ADSP-217x provides 2K words (24-bit) of program RAM
and 2K words (16-bit) of data memory. T he ADSP-2172 pro-
vides an additional 8K words (24-bit) of program ROM. Power-
down circuitry is also provided to meet the low power needs of
battery operated portable equipment. T he ADSP-217x is avail-
able in 128-pin T QFP and 128-pin PQFP packages.
Fabricated in a high-speed, double metal, low power, CMOS
process, the ADSP-217X operates with a 30 ns instruction cycle
time. Every instruction can execute in a single processor cycle.
T he ADSP-217x’s flexible architecture and comprehensive in-
struction set allow the processor to perform multiple operations
in parallel. In one processor cycle the ADSP-217x can:
Multifunction Instructions
Three Edge- or Level-Sensitive External Interrupts
Low Pow er Dissipation in Standby Mode
128-Lead TQFP and 128-Lead PQFP
• generate the next program address
• fetch the next instruction
GENERAL D ESCRIP TIO N
• perform one or two data moves
• update one or two data address pointers
• perform a computational operation
T he ADSP-2171, ADSP-2172, and ADSP-2173 are single-chip
microcomputers optimized for digital signal processing (DSP)
and other high-speed numeric processing applications. T he
ADSP-2171 and ADSP-2172 are designed for 5.0 V applica-
tions. T he ADSP-2173 is designed for 3.3 V applications. T he
ADSP-2172 also has 8K words (24-bit) of program ROM.
T his takes place while the processor continues to:
• receive and transmit data through the two serial ports
• receive and/or transmit data through the host interface port
REV. A
• decrement timer
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
© Analog Devices, Inc., 1995
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
Tel: 617/ 329-4700
Fax: 617/ 326-8703
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