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ADSP-21469KBCZ-3 PDF预览

ADSP-21469KBCZ-3

更新时间: 2024-02-18 18:39:53
品牌 Logo 应用领域
亚德诺 - ADI 微控制器和处理器外围集成电路数字信号处理器时钟
页数 文件大小 规格书
72页 2169K
描述
SHARC Processor

ADSP-21469KBCZ-3 技术参数

是否无铅:含铅是否Rohs认证:符合
生命周期:Active零件包装代码:BGA
包装说明:BGA, BGA324,18X18,40针数:324
Reach Compliance Code:compliantECCN代码:3A991.A.2
HTS代码:8542.31.00.01风险等级:1.6
Is Samacsys:N地址总线宽度:24
桶式移位器:YES位大小:32
边界扫描:YES最大时钟频率:66.66 MHz
外部数据总线宽度:8格式:FLOATING POINT
内部总线架构:MULTIPLEJESD-30 代码:S-PBGA-B324
JESD-609代码:e1长度:19 mm
低功率模式:NO端子数量:324
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:BGA
封装等效代码:BGA324,18X18,40封装形状:SQUARE
封装形式:GRID ARRAY峰值回流温度(摄氏度):260
电源:1.05,1.8,3.3 V认证状态:Not Qualified
RAM(字数):163840座面最大高度:1.8 mm
子类别:Digital Signal Processors最大压摆率:10 mA
最大供电电压:1.1 V最小供电电压:1 V
标称供电电压:1.05 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Silver/Copper (Sn/Ag/Cu)端子形式:BALL
端子节距:1 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:40宽度:19 mm
uPs/uCs/外围集成电路类型:DIGITAL SIGNAL PROCESSOR, MIXEDBase Number Matches:1

ADSP-21469KBCZ-3 数据手册

 浏览型号ADSP-21469KBCZ-3的Datasheet PDF文件第2页浏览型号ADSP-21469KBCZ-3的Datasheet PDF文件第3页浏览型号ADSP-21469KBCZ-3的Datasheet PDF文件第4页浏览型号ADSP-21469KBCZ-3的Datasheet PDF文件第5页浏览型号ADSP-21469KBCZ-3的Datasheet PDF文件第6页浏览型号ADSP-21469KBCZ-3的Datasheet PDF文件第7页 
SHARC Processor  
ADSP-21469  
SUMMARY  
High performance 32-bit/40-bit floating-point processor  
optimized for high performance audio processing  
Single-instruction, multiple-data (SIMD) computational  
architecture  
5 Mbits of on-chip RAM, 4 Mbits of on-chip ROM  
Up to 450 MHz operating frequency  
The ADSP-21469 processor is available with unique audio-  
centric peripherals such as the digital applications  
interface, DTCP (digital transmission content protection  
protocol), serial ports, precision clock generators, S/PDIF  
transceiver, asynchronous sample rate converters, input  
data port, and more.  
For complete ordering information, see Ordering Guide on  
Page 70  
Qualified for automotive applications, see Automotive Prod-  
ucts on Page 70  
Code compatible with all other members of the SHARC family  
Internal Memory  
SIMD Core  
Block 0  
RAM/ROM  
Block 1  
RAM/ROM  
Block 2  
RAM  
Block 3  
RAM  
Instruction  
Cache  
5 Stage  
Sequencer  
B2D  
64-BIT  
B0D  
64-BIT  
B3D  
64-BIT  
B1D  
64-BIT  
S
DAG1/2  
PEx  
Timer  
PEy  
DMD  
64-BIT  
DMD  
64-BIT  
Core Bus  
Cross Bar  
Internal Memory I/F  
PMD 64-BIT  
PMD  
64-BIT  
FLAGx/IRQx/  
TMREXP  
THERMAL  
DIODE  
IOD0 32-BIT  
EPD BUS 64-BIT  
JTAG  
IOD1  
32-BIT  
PERIPHERAL  
BUS 32-BIT  
IOD0 BUS  
FFT  
DTCP/  
MTM  
FIR  
IIR  
PERIPHERAL BUS  
EP  
SPEP BUS  
LINK  
PORT  
1-0  
PDAP/  
IDP  
7-0  
S/PDIF PCG ASRC  
Tx/Rx  
SPORT  
7-0  
CORE PCG  
FLAGS  
TIMER  
CORE PWM  
DDR2  
CTL  
TWI  
SPI/B  
UART  
AMI  
MLB  
C
-
D
1-  
0
A
-
D
3
-
0
FLAGS  
3-0  
External  
Port  
DPI Routing/Pins  
DAI Routing/Pins  
External Port Pin MUX  
DPI Peripherals  
DAI Peripherals  
Peripherals  
Figure 1. Functional Block Diagram  
SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.  
Rev. 0  
Information furnished by Analog Devices is believed to be accurate and reliable.  
However, no responsibility is assumed by Analog Devices for its use, nor for any  
infringements of patents or other rights of third parties that may result from its use.  
Specifications subject to change without notice. No license is granted by implication  
or otherwise under any patent or patent rights of Analog Devices. Trademarks and  
registered trademarks are the property of their respective companies.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.  
Tel: 781.329.4700  
Fax: 781.326.3113  
www.analog.com  
©2010 Analog Devices, Inc. All rights reserved.  

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