SHARC Processors
ADSP-21367/ADSP-21368/ADSP-21369
SUMMARY
DEDICATED AUDIO COMPONENTS
High performance 32-bit/40-bit floating-point processor
optimized for high performance audio processing
Single-instruction, multiple-data (SIMD) computational
architecture
On-chip memory—2M bits of on-chip SRAM and 6M bits of
on-chip mask programmable ROM
S/PDIF-compatible digital audio receiver/transmitter
4 independent asynchronous sample rate converters (SRC)
16 PWM outputs configured as four groups of four outputs
ROM-based security features include
JTAG access to memory permitted with a 64-bit key
Protected memory regions that can be assigned to limit
Code compatible with all other members of the SHARC family
The ADSP-21367/ADSP-21368/ADSP-21369 are available
with a 400 MHz core instruction rate with unique audiocen-
tric peripherals such as the digital applications interface,
S/PDIF transceiver, serial ports, 8-channel asynchronous
sample rate converter, precision clock generators, and
more. For complete ordering information, see Ordering
Guide on Page 58.
access under program control to sensitive code
PLL has a wide variety of software and hardware multi-
plier/divider ratios
Available in 256-ball BGA_ED and 208-lead LQFP_EP
packages
Internal Memory
SIMD Core
Block 0
RAM/ROM
Block 1
RAM/ROM
Block 2
RAM
Block 3
RAM
Instruction
Cache
5 stage
Sequencer
B2D
64-BIT
B0D
64-BIT
B3D
64-BIT
B1D
64-BIT
S
DAG1/2
PEx
Timer
PEy
DMD
64-BIT
DMD 64-BIT
Core Bus
Cross Bar
Internal Memory I/F
PMD 64-BIT
PMD
64-BIT
IOD0 32-BIT
FLAGx/IRQx/
TMREXP
EPD BUS 32-BIT
JTAG
PERIPHERAL BUS
32-BIT
IOD1
32-BIT
IOD0 BUS
MTM
PERIPHERAL BUS
EP
IDP/
PDAP
7-0
S/PDIF PCG ASRC
SPORT
7-0
CORE PCG
FLAGS
TIMER
UART
CORE PWM
TWI
SPI/B
AMI
SDRAM
Tx/Rx
A
-D
3
-0
C
-
D
2
-0
1
-0
FLAGS
3-0
DPI Routing/Pins
DAI Routing/Pins
External Port Pin MUX
External
Port
DPI Peripherals
DAI Peripherals
Peripherals
Figure 1. Functional Block Diagram
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