SHARC® Processor
ADSP-21367
processor algorithm combination support will vary
depending upon the chip version and the system configu-
rations. Please visit www.analog.com
Single-Instruction Multiple-Data (SIMD) computational
architecture
On-chip memory—2M bit of on-chip SRAM and a dedicated
6M bit of on-chip mask-programmable ROM
Code compatible with all other members of the SHARC family
The ADSP-21367 is available with a 400 MHz core instruction
rate with unique audio centric peripherals such as the Digi-
tal Audio Interface, S/PDIF transceiver, serial ports, 8-
channel asynchronous sample rate converter, precision
clock generators and more. For complete ordering infor-
mation, see Ordering Guide on page 47
a
Preliminary Technical Data
SUMMARY
High performance 32-bit/40-bit floating point processor
optimized for high performance automotive audio
processing
Audio decoder and post processor-algorithm support with
32-bit floating-point implementations
Non-volatile memory may be configured to support audio
decoders and post processor-algorithms like PCM, Dolby
Digital EX, Dolby Prologic IIx, Dolby Digital Plus, Dolby
headphone, DTS 96/24, Neo:6, DTS ES, DTS Lossless,
MPEG2 AAC, MPEG2 2channel, MP3, WMAPro, and Multi-
channel encoder. Functions like Bass management, Delay,
Speaker equalization, Graphic equalization, Decoder/post-
JTAG TEST & EMULATION
4 BLOCKS OF
CORE PROCESSOR
INSTRUCTION
ON-CHIP MEMORY
EXTERNAL PORT
24
CACHE
32 X 48-BIT
TIMER
2 M BIT RAM, 6 M BI T RO M
8
3
ADDRESS
11
SDRAM
CONTROLLER
ADDR
DATA
DAG2
8X4X32
ASYNCHRONOUS
ME MO RY
INTERFACE
DAG1
8X4X32
PROGRAM
SEQUENCER
CONTROL
32
DATA
32
PM ADDRESS BUS
DMADDRESS BUS
PM DATA BUS
32
64
64
DM DATA BUS
IOD(32)
IOA(24)
DMA
CONTROLLER
PROCESSING
EL EMENT
(P EX)
PX REGISTER
PROCESSING
ELEMENT
(PEY)
IOP REGIST ER (MEMORY MAPPED)
CONTROL, STATUS, & DATA BUFFERS
34 CHANNELS
ME MORY -T O-
ME MORY DMA (2 )
PWM (16)
PRECISION CLOCK
GENERATORS (4)
SERIAL PORTS (8)
SPI PORT (2)
4
UART (2)
GPIO FLAGS/
IRQ/TIMEXP
INPUT DATA PORT/
PDAP
TWO WIRE
INTERFACE
SRC (8 CHANNELS)
SPDIF (RX/TX)
TIMERS (3)
DAI PINS
DPI PINS
S
DIGITAL PERIP HE RAL INTE RFACE
DIGITAL AUDIO INTERFACE
I/O PROCESSOR
14
20
Figure 1. Functional Block Diagram – Processor Core
SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.
Rev. PrA
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