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ADSP-21363SBBC-ENG PDF预览

ADSP-21363SBBC-ENG

更新时间: 2024-02-26 22:04:14
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
44页 413K
描述
SHARC Processor

ADSP-21363SBBC-ENG 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:QFP
包装说明:LEAD FREE, MS-026BFB-HD, LQFP-144针数:144
Reach Compliance Code:compliantECCN代码:3A001.A.3
HTS代码:8542.31.00.01风险等级:5.77
Is Samacsys:N其他特性:ALSO REQUIRES 3.3V SUPPLY
地址总线宽度:16桶式移位器:YES
边界扫描:YES最大时钟频率:55.55 MHz
外部数据总线宽度:16格式:FLOATING POINT
内部总线架构:MULTIPLEJESD-30 代码:S-PQFP-G144
JESD-609代码:e3长度:20 mm
低功率模式:NO端子数量:144
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:HLFQFP
封装形状:SQUARE封装形式:FLATPACK, HEAT SINK/SLUG, LOW PROFILE, FINE PITCH
峰值回流温度(摄氏度):NOT SPECIFIED认证状态:Not Qualified
座面最大高度:1.6 mm最大供电电压:1.26 V
最小供电电压:1.14 V标称供电电压:1.2 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:20 mmuPs/uCs/外围集成电路类型:DIGITAL SIGNAL PROCESSOR, OTHER
Base Number Matches:1

ADSP-21363SBBC-ENG 数据手册

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SHARC® Processor  
ADSP-21363  
On-chip memory—3M bit of on-chip SRAM and a dedicated  
4M bit of on-chip mask-programmable ROM  
Code compatible with all other members of the SHARC family  
The ADSP-21363 is available with a 333 MHz core instruction  
rate. For complete ordering information, see Ordering  
Guide on Page 44  
a
Preliminary Technical Data  
SUMMARY  
High performance 32-bit/40-bit floating point processor  
optimized for professional audio processing  
At 333 MHz/2 GFLOPs, with unique audio centric peripherals  
such as the Digital Audio Interface the ADSP-21363 SHARC  
processor is ideal for applications that require industry  
leading equalization, reverberation and other effects  
processing  
Single-Instruction Multiple-Data (SIMD) computational  
architecture  
Two 32-bit IEEE floating-point/32-bit fixed-point/40-bit  
extended precision floating-point computational units,  
each with a multiplier, ALU, shifter, and register file  
4 BLOCKS OF ON-CHIP MEMORY  
CORE PROCESSOR  
INSTRUCTION  
BLOCK 0  
SRAM  
1M BIT ROM  
2M BIT  
BLOCK 1  
BLOCK 2  
BLOCK 3  
SRAM  
1M BIT  
CACHE  
TIMER  
SRAM  
0.5M BIT  
SRAM  
0.5M BIT  
ROM  
2M BIT  
32 X 48-BIT  
ADDR  
DATA  
ADDR  
DATA  
ADDR  
DATA  
ADDR  
DATA  
DAG1  
8X4X32  
DAG2  
8X4X32  
PROGRAM  
SEQUENCER  
32  
PM ADDRESS BUS  
32  
64  
DM ADDRESS BUS  
PM DATA BUS  
64  
DM DATA BUS  
IOA  
IOD  
IOA  
IOD  
IOA  
IOD  
IOA  
IOD  
PX REGISTER  
PROCESSING  
ELEMENT  
(PEX)  
PROCESSING  
ELEMENT  
(PEY)  
SPI  
SPORTS  
IDP  
PCG  
IOP REGISTERS  
(MEMORY MAPPED)  
SIGNAL  
ROUTING  
UNIT  
TIMERS  
6
JTAG TEST & EMULATION  
I/O PROCESSOR  
AND PERIPHERALS  
SEE “ADSP-21363 MEMORY  
AND I/O INTERFACE FEATURES”  
SECTION FOR DETAILS  
S
Figure 1. Functional Block Diagram – Processor Core  
SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.  
Rev. PrA  
Information furnished by Analog Devices is believed to be accurate and reliable.  
However, no responsibility is assumed by Analog Devices for its use, nor for any  
infringements of patents or other rights of third parties that may result from its use.  
Specifications subject to change without notice. No license is granted by implication  
or otherwise under any patent or patent rights of Analog Devices. Trademarks and  
registered trademarks are the property of their respective companies.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.  
Tel:781.329.4700  
Fax:781.326.8703  
www.analog.com  
© 2004 Analog Devices, Inc. All rights reserved.  

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