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ADSP-21262SKSTZ200 PDF预览

ADSP-21262SKSTZ200

更新时间: 2024-02-08 09:15:31
品牌 Logo 应用领域
亚德诺 - ADI 微控制器和处理器外围集成电路数字信号处理器PC时钟
页数 文件大小 规格书
44页 1303K
描述
SHARC Processor

ADSP-21262SKSTZ200 技术参数

是否无铅: 含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:QFP
包装说明:LFQFP, QFP144,.87SQ,20针数:144
Reach Compliance Code:compliantECCN代码:3A991.A.2
HTS代码:8542.31.00.01风险等级:8.46
Samacsys Confidence:3Samacsys Status:Released
2D Presentation:https://componentsearchengine.com/2D/0T/243307.1.1.pngSchematic Symbol:https://componentsearchengine.com/symbol.php?partID=243307
PCB Footprint:https://componentsearchengine.com/footprint.php?partID=2433073D View:https://componentsearchengine.com/viewer/3D.php?partID=243307
Samacsys PartID:243307Samacsys Image:https://componentsearchengine.com/Images/9/ADSP-21262SKSTZ200.jpg
Samacsys Thumbnail Image:https://componentsearchengine.com/Thumbnails/1/ADSP-21262SKSTZ200.jpgSamacsys Pin Count:144
Samacsys Part Category:Integrated CircuitSamacsys Package Category:Quad Flat Packages
Samacsys Footprint Name:ST-144 (LQFP)Samacsys Released Date:2018-11-02 12:21:19
Is Samacsys:N地址总线宽度:16
桶式移位器:YES位大小:32
边界扫描:YES最大时钟频率:66.67 MHz
外部数据总线宽度:16格式:FLOATING POINT
内部总线架构:MULTIPLEJESD-30 代码:S-PQFP-G144
JESD-609代码:e3长度:20 mm
低功率模式:NO湿度敏感等级:3
端子数量:144最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:LFQFP封装等效代码:QFP144,.87SQ,20
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE, FINE PITCH
峰值回流温度(摄氏度):260电源:1.2,3.3 V
认证状态:Not QualifiedRAM(字数):65536
座面最大高度:1.6 mm子类别:Digital Signal Processors
最大供电电压:1.26 V最小供电电压:1.14 V
标称供电电压:1.2 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:40宽度:20 mm
uPs/uCs/外围集成电路类型:DIGITAL SIGNAL PROCESSOR, OTHERBase Number Matches:1

ADSP-21262SKSTZ200 数据手册

 浏览型号ADSP-21262SKSTZ200的Datasheet PDF文件第2页浏览型号ADSP-21262SKSTZ200的Datasheet PDF文件第3页浏览型号ADSP-21262SKSTZ200的Datasheet PDF文件第4页浏览型号ADSP-21262SKSTZ200的Datasheet PDF文件第5页浏览型号ADSP-21262SKSTZ200的Datasheet PDF文件第6页浏览型号ADSP-21262SKSTZ200的Datasheet PDF文件第7页 
SHARC® Processor  
ADSP-21262  
DAI incorporates two precision clock generators (PCGs), an  
input data port (IDP) which includes the parallel data  
acquisition port (PDAP), and three programmable timers,  
all under software control through the signal routing unit  
(SRU)  
On-chip memory—2M bits of on-chip SRAM and a dedicated  
4M bits of on-chip mask-programmable ROM  
Six independent synchronous serial ports provide a variety  
of serial communication protocols including TDM and I2S  
modes  
The ADSP-21262 is available with a 200 MHz core instruction  
rate. For complete ordering information, see Ordering  
Guide on Page 44.  
SUMMARY  
High performance 32-bit/40-bit floating-point processor  
optimized for high precision signal processing  
applications  
The ADSP-21262 SHARC DSP is code compatible with all  
other SHARC DSPs  
Single-Instruction Multiple-Data (SIMD) computational archi-  
tecture—two 32-bit IEEE floating-point/32-bit fixed-  
point/40-bit extended precision floating-point computa-  
tional units, each with a multiplier, ALU, shifter, and  
register file  
High bandwidth I/O—A parallel port, SPI port, six serial  
ports, digital audio interface (DAI), and JTAG  
DUAL PORTED MEMORY  
BLOCK 0  
DUAL PORTED MEMORY  
BLO CK 1  
CORE PROCESSOR  
INSTRUCTION  
SRAM  
SRAM  
CACHE  
TIMER  
1 MBIT  
ROM  
1 MBIT  
ROM  
32 
؋
 48-BIT  
2 MBIT  
2 MBIT  
DAG1  
8 
؋
 4 
؋
 32  
DAG2  
8 
؋
 4 
؋
 32  
PROGRAM  
SEQUENCER  
ADDR  
DATA  
ADDR  
DATA  
32  
32  
P M ADDRES S BUS  
DM ADDRESS BUS  
64  
64  
PM DATA BUS  
DM DATA BUS  
IOD  
(32)  
IOA  
(18)  
DMA CONTROLLER  
PX REGISTER  
4
22 CHANNE LS  
GPIO FLAGS/  
IRQ/TIMEXP  
PROCESSING  
EL EMENT  
(PEX)  
PROCESSING  
ELEMENT  
(PEY)  
4
SPI PORT (1)  
16  
ADDRES S/  
DATA BUS / GPIO  
3
6
CONTROL/GP IO  
SERIAL PORTS (6)  
JTAG TEST & EMULATION  
PARALLEL  
PORT  
IOP  
REGISTERS  
(MEMORY MAPPED)  
20  
SIGNAL  
RO UTI NG  
UNIT  
INPUT  
DATA PORTS (8)  
PARALLEL DATA  
ACQUISITION PORT  
CO NTROL,  
STATUS,  
DATA BUFFERS  
PRECISION CLOCK  
GENERATORS (2)  
S
3
TIMERS (3)  
DIGITAL AUDIO INTERFACE  
I/O PROCESSOR  
Figure 1. Functional Block Diagram  
SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.  
Rev. A  
Information furnished by Analog Devices is believed to be accurate and reliable.  
However, no responsibility is assumed by Analog Devices for its use, nor for any  
infringements of patents or other rights of third parties that may result from its use.  
Specifications subject to change without notice. No license is granted by implication  
or otherwise under any patent or patent rights of Analog Devices. Trademarks and  
registered trademarks are the property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.  
Tel: 781.329.4700  
Fax: 781.326.8703  
www.analog.com  
© 2004 Analog Devices, Inc. All rights reserved.  

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