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ADSP-21261SKBCZ150 PDF预览

ADSP-21261SKBCZ150

更新时间: 2024-02-14 06:18:08
品牌 Logo 应用领域
亚德诺 - ADI 微控制器和处理器外围集成电路数字信号处理器时钟
页数 文件大小 规格书
44页 1232K
描述
SHARC Embedded Processor

ADSP-21261SKBCZ150 技术参数

是否无铅: 含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:BGA
包装说明:LFBGA, BGA136,14X14,32针数:136
Reach Compliance Code:compliantECCN代码:3A991.A.2
HTS代码:8542.31.00.01风险等级:8.2
Is Samacsys:N其他特性:ALSO REQUIRES 3.3V SUPPLY
地址总线宽度:16桶式移位器:YES
位大小:32边界扫描:YES
最大时钟频率:50 MHz外部数据总线宽度:16
格式:FLOATING POINT内部总线架构:MULTIPLE
JESD-30 代码:S-PBGA-B136JESD-609代码:e1
长度:12 mm低功率模式:NO
湿度敏感等级:3端子数量:136
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:LFBGA
封装等效代码:BGA136,14X14,32封装形状:SQUARE
封装形式:GRID ARRAY, LOW PROFILE, FINE PITCH峰值回流温度(摄氏度):260
电源:1.2,3.3 V认证状态:Not Qualified
RAM(字数):49152座面最大高度:1.7 mm
子类别:Digital Signal Processors最大供电电压:1.26 V
最小供电电压:1.14 V标称供电电压:1.2 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Silver/Copper (Sn96.5Ag3.0Cu0.5)
端子形式:BALL端子节距:0.8 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:40
宽度:12 mmuPs/uCs/外围集成电路类型:DIGITAL SIGNAL PROCESSOR, OTHER
Base Number Matches:1

ADSP-21261SKBCZ150 数据手册

 浏览型号ADSP-21261SKBCZ150的Datasheet PDF文件第2页浏览型号ADSP-21261SKBCZ150的Datasheet PDF文件第3页浏览型号ADSP-21261SKBCZ150的Datasheet PDF文件第4页浏览型号ADSP-21261SKBCZ150的Datasheet PDF文件第5页浏览型号ADSP-21261SKBCZ150的Datasheet PDF文件第6页浏览型号ADSP-21261SKBCZ150的Datasheet PDF文件第7页 
SHARC®  
Embedded Processor  
a
ADSP-21261  
SUMMARY  
KEY FEATURES  
High performance 32-bit/40-bit floating-point processor  
Code compatibility—at assembly level, uses the same  
instruction set as other SHARC DSPs  
Serial ports offer left-justified sample-pair and I2S support  
via 12 programmable and simultaneous receive or trans-  
mit pins, which support up to 24 transmit or 24 receive I2S  
channels of audio when all four serial ports (SPORTs) are  
enabled or six full duplex TDM streams of up to 128  
channels per frame  
At 150 MHz (6.67 ns) core instruction rate, the ADSP-21261  
operates at 900 MFLOPS peak/600 MFLOPS sustained per-  
formance whether operating on fixed- or floating-point  
data  
300 MMACS sustained performance at 150 MHz  
Super Harvard Architecture—three independent buses for  
dual data fetch, instruction fetch, and nonintrusive, zero-  
overhead I/O  
Transfers between memory and core at up to four 32-bit  
floating- or fixed-point words per cycle, sustained  
1.8G byte/s bandwidth at 150 MHz core instruction rate  
and 900M byte/s is available via DMA  
Single-instruction multiple-data (SIMD) computational archi-  
tecture—two 32-bit IEEE floating-point/32-bit fixed-point/  
40-bit extended precision floating-point computational  
units, each with a multiplier, ALU, shifter, and register file  
High bandwidth I/O—a parallel port, an SPI® port, four serial  
ports, a digital applications interface (DAI), and JTAG  
DAI incorporates two precision clock generators (PCGs), an  
input data port (IDP) that includes a parallel data acquisi-  
tion port (PDAP), and three programmable timers, all  
under software control by the signal routing unit (SRU)  
On-chip memory—1M bit of on-chip SRAM and a dedicated  
3M bit of on-chip mask-programmable ROM  
The ADSP-21261 is available in commercial and industrial  
temperature grades. For complete ordering information,  
see Ordering Guide on Page 44.  
DUAL PORTED MEMORY  
BLOCK 0  
DUAL PORTED MEMORY  
BLOCK 1  
CORE PROCESSOR  
INSTRUCTION  
CACHE  
32 
؋
 48-BIT  
TIMER  
SRAM  
0. 5M BIT  
SRAM  
0.5M BIT  
RO M  
ROM  
1. 5M BIT  
1.5M BIT  
DAG1  
8 
؋
 4 
؋
 32  
DAG2  
8 
؋
 4 
؋
 32  
PROGRAM  
SEQ UENCER  
ADDR  
DATA  
ADDR  
DATA  
32  
32  
PM ADDRESS BUS  
DM ADDRESS BUS  
64  
64  
PM DATA BUS  
DM DATA BUS  
IOD  
(32)  
IOA  
(18)  
DMA CONTROLLER  
PX REGISTER  
4
18 CHANNE LS  
GPIO FLAGS/  
IRQ/TIMEXP  
PROCESSING  
ELEMENT  
(PEX)  
PROCESSING  
ELEMENT  
(PEY)  
4
SPI PORT (1)  
16  
ADDRES S/  
DATA BUS /GPIO  
3
6
CONTROL/GPIO  
SERIAL PORTS (4)  
JTAG TEST & EMULATION  
PARALLEL  
PORT  
IOP  
REGISTERS  
20  
SIGNAL  
RO UTI NG  
UNIT  
INPUT  
(MEMORY MAPPED)  
DATA PORTS (8)  
PARALLEL DATA  
ACQUISITION PORT  
CONTROL,  
STATUS,  
DATA BUFFERS  
PRECISION CLOCK  
GENERATORS (2)  
S
3
TIMERS (3)  
DIGITAL APPLICATIONS INTERFACE  
I/O PROCESSOR  
Figure 1. Functional Block Diagram  
SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.  
Rev. 0  
Information furnished by Analog Devices is believed to be accurate and reliable.  
However, no responsibility is assumed by Analog Devices for its use, nor for any  
infringements of patents or other rights of third parties that may result from its use.  
Specifications subject to change without notice. No license is granted by implication  
or otherwise under any patent or patent rights of Analog Devices. Trademarks and  
registered trademarks are the property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Fax: 781.461.3113  
www.analog.com  
© 2006 Analog Devices, Inc. All rights reserved.  

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