SHARC®
Embedded Processor
a
ADSP-21261
SUMMARY
KEY FEATURES
High performance 32-bit/40-bit floating-point processor
Code compatibility—at assembly level, uses the same
instruction set as other SHARC DSPs
Serial ports offer left-justified sample-pair and I2S support
via 12 programmable and simultaneous receive or trans-
mit pins, which support up to 24 transmit or 24 receive I2S
channels of audio when all four serial ports (SPORTs) are
enabled or six full duplex TDM streams of up to 128
channels per frame
At 150 MHz (6.67 ns) core instruction rate, the ADSP-21261
operates at 900 MFLOPS peak/600 MFLOPS sustained per-
formance whether operating on fixed- or floating-point
data
300 MMACS sustained performance at 150 MHz
Super Harvard Architecture—three independent buses for
dual data fetch, instruction fetch, and nonintrusive, zero-
overhead I/O
Transfers between memory and core at up to four 32-bit
floating- or fixed-point words per cycle, sustained
1.8G byte/s bandwidth at 150 MHz core instruction rate
and 900M byte/s is available via DMA
Single-instruction multiple-data (SIMD) computational archi-
tecture—two 32-bit IEEE floating-point/32-bit fixed-point/
40-bit extended precision floating-point computational
units, each with a multiplier, ALU, shifter, and register file
High bandwidth I/O—a parallel port, an SPI® port, four serial
ports, a digital applications interface (DAI), and JTAG
DAI incorporates two precision clock generators (PCGs), an
input data port (IDP) that includes a parallel data acquisi-
tion port (PDAP), and three programmable timers, all
under software control by the signal routing unit (SRU)
On-chip memory—1M bit of on-chip SRAM and a dedicated
3M bit of on-chip mask-programmable ROM
The ADSP-21261 is available in commercial and industrial
temperature grades. For complete ordering information,
see Ordering Guide on Page 44.
DUAL PORTED MEMORY
BLOCK 0
DUAL PORTED MEMORY
BLOCK 1
CORE PROCESSOR
INSTRUCTION
CACHE
TIMER
SRAM
0. 5M BIT
SRAM
0.5M BIT
RO M
ROM
1. 5M BIT
1.5M BIT
DAG1
DAG2
PROGRAM
SEQ UENCER
ADDR
DATA
ADDR
DATA
32
32
PM ADDRESS BUS
DM ADDRESS BUS
64
64
PM DATA BUS
DM DATA BUS
IOD
(32)
IOA
(18)
DMA CONTROLLER
PX REGISTER
4
18 CHANNE LS
GPIO FLAGS/
IRQ/TIMEXP
PROCESSING
ELEMENT
(PEX)
PROCESSING
ELEMENT
(PEY)
4
SPI PORT (1)
16
ADDRES S/
DATA BUS /GPIO
3
6
CONTROL/GPIO
SERIAL PORTS (4)
JTAG TEST & EMULATION
PARALLEL
PORT
IOP
REGISTERS
20
SIGNAL
RO UTI NG
UNIT
INPUT
(MEMORY MAPPED)
DATA PORTS (8)
PARALLEL DATA
ACQUISITION PORT
CONTROL,
STATUS,
DATA BUFFERS
PRECISION CLOCK
GENERATORS (2)
S
3
TIMERS (3)
DIGITAL APPLICATIONS INTERFACE
I/O PROCESSOR
Figure 1. Functional Block Diagram
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Rev. 0
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