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ADSP-21160NCB-TBD PDF预览

ADSP-21160NCB-TBD

更新时间: 2024-02-01 03:22:28
品牌 Logo 应用领域
亚德诺 - ADI 微控制器和处理器数字信号处理器电脑
页数 文件大小 规格书
53页 1556K
描述
DSP Microcomputer

ADSP-21160NCB-TBD 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
Reach Compliance Code:unknown风险等级:5.92
位大小:32格式:FLOATING-POINT
JESD-30 代码:S-PBGA-B400端子数量:400
封装主体材料:PLASTIC/EPOXY封装代码:BGA
封装等效代码:BGA400,20X20,50封装形状:SQUARE
封装形式:GRID ARRAY电源:1.9,3.3 V
认证状态:Not QualifiedRAM(字数):131072
子类别:Digital Signal Processors表面贴装:YES
技术:CMOS端子形式:BALL
端子节距:1.27 mm端子位置:BOTTOM
Base Number Matches:1

ADSP-21160NCB-TBD 数据手册

 浏览型号ADSP-21160NCB-TBD的Datasheet PDF文件第2页浏览型号ADSP-21160NCB-TBD的Datasheet PDF文件第3页浏览型号ADSP-21160NCB-TBD的Datasheet PDF文件第4页浏览型号ADSP-21160NCB-TBD的Datasheet PDF文件第5页浏览型号ADSP-21160NCB-TBD的Datasheet PDF文件第6页浏览型号ADSP-21160NCB-TBD的Datasheet PDF文件第7页 
PRELIMINARY TECHNICAL DATA  
a
DSP Microcomputer  
ADSP-21160N  
Preliminary Technical Data  
SUMMARY  
KEY FEATURES  
High-Performance 32-Bit DSP—Applications in Audio,  
Medical, Military, Graphics, Imaging, and  
Communication  
Super Harvard Architecture—Four Independent Buses  
for Dual Data Fetch, Instruction Fetch, and  
Nonintrusive, Zero-Overhead I/O  
Backwards-Compatible—Assembly Source Level  
Compatible with Code for ADSP-2106x DSPs  
Single-Instruction-Multiple-Data (SIMD) Computational  
Architecture—Two 32-Bit IEEE Floating-Point  
Computation Units, Each with a Multiplier, ALU,  
Shifter, and Register File  
95 MHz (10.5 ns) Core Instruction Rate  
Single-Cycle Instruction Execution, Including SIMD  
Operations in Both Computational Units  
570 MFLOPS Peak and 380 MFLOPS Sustained  
Performance (Based on FIR)  
Dual Data Address Generators (DAGs) with Modulo and  
Bit-Reverse Addressing  
Zero-Overhead Looping and Single-Cycle Loop Setup,  
Providing Efficient Program Sequencing  
IEEE 1149.1 JTAG Standard Test Access Port and  
On-Chip Emulation  
400-Ball 27 
؋
 27 mm Metric PBGA Package  
Integrated Peripherals—Integrated I/O Processor,  
4M Bits On-Chip Dual-Ported SRAM, Glueless  
Multiprocessing Features, and Ports (Serial, Link,  
External Bus, and JTAG)  
FUNCTIONAL BLOCK DIAGRAM  
CORE PROCESSOR  
TIMER  
DUAL-PORTED SRAM  
JTAG  
INSTRUCTION  
CACHE  
32 X 48-BIT  
TWO INDEPENDENT  
DUAL-PORTED BLOCKS  
6
TEST AND  
EMULATION  
PROCESSOR PORT  
ADDR DATA  
ADDR  
I/O PORT  
DATA ADDR  
DATA  
ADDR  
DATA  
DAG2  
8X4X32  
DAG1  
8X4X32  
PROGRAM  
SEQUENCER  
EXTERNAL  
PORT  
IOD  
64  
IOA  
18  
PM ADDRESS BUS  
32  
32  
32  
64  
ADDR BUS  
MUX  
DM ADDRESS BUS  
MULTIPROCESSOR  
INTERFACE  
PM DATA BUS  
DM DATA BUS  
16/32/40/48/64  
32/40/64  
BUS  
CONNECT  
(PX)  
DATA BUS  
MUX  
HOST PORT  
DATA  
DATA  
REGISTER  
REGISTER  
FILE  
(PEX)  
16 X 40-BIT  
FILE  
(PEY)  
16 X 40-BIT  
4
DMA  
CONTROLLER  
IOP  
BARREL  
SHIFTER  
BARREL  
SHIFTER  
MULT  
MULT  
REGISTERS  
(MEMORY  
MAPPED)  
6
6
SERIAL PORTS  
(2)  
CONTROL,  
STATUS, AND  
DATA BUFFERS  
60  
LINK PORTS  
(6)  
ALU  
ALU  
I/O PROCESSOR  
REV. PrB  
This information applies to a product under development. Its characteristics and speci- One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106, U.S.A.  
fications are subject to change without notice. Analog Devices  
Tel:781/329-4700  
www.analog.com  
©Analog Devices,Inc., 2002  
assumes no obligation regarding future manufacturing unless otherwise agreed to in Fax:781/326-8703  
writing.  

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