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ADSP-2109KP-80 PDF预览

ADSP-2109KP-80

更新时间： 2024-01-16 01:16:03
品牌 Logo 应用领域
亚德诺 - ADI 微控制器和处理器外围集成电路数字信号处理器计算机时钟
页数 文件大小 规格书
36页 334K
描述
Low Cost DSP Microcomputers

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ADSP-2109KP-80 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：LCC包装说明：QCCJ, LDCC68,1.0SQ
针数：68Reach Compliance Code：not_compliant
ECCN代码：EAR99HTS代码：8542.31.00.01
风险等级：5.92地址总线宽度：14
桶式移位器：YES位大小：16
边界扫描：NO最大时钟频率：20 MHz
外部数据总线宽度：24格式：FIXED POINT
内部总线架构：MULTIPLEJESD-30 代码：R-PQCC-J68
JESD-609代码：e0长度：24.18 mm
低功率模式：YES端子数量：68
最高工作温度：70 °C最低工作温度：
封装主体材料：PLASTIC/EPOXY封装代码：QCCJ
封装等效代码：LDCC68,1.0SQ封装形状：RECTANGULAR
封装形式：CHIP CARRIER峰值回流温度（摄氏度）：NOT SPECIFIED
电源：5 V认证状态：Not Qualified
RAM（字数）：256座面最大高度：4.45 mm
子类别：Digital Signal Processors最大压摆率：31 mA
最大供电电压：3.6 V最小供电电压：3 V
标称供电电压：3.3 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：J BEND
端子节距：1.27 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：24.18 mm
uPs/uCs/外围集成电路类型：DIGITAL SIGNAL PROCESSOR, OTHERBase Number Matches：1

ADSP-2109KP-80 数据手册

 浏览型号ADSP-2109KP-80的Datasheet PDF文件第2页浏览型号ADSP-2109KP-80的Datasheet PDF文件第3页浏览型号ADSP-2109KP-80的Datasheet PDF文件第4页浏览型号ADSP-2109KP-80的Datasheet PDF文件第5页浏览型号ADSP-2109KP-80的Datasheet PDF文件第6页浏览型号ADSP-2109KP-80的Datasheet PDF文件第7页 
a
Low Cost DSP Microcomputers  
ADSP-2104/ADSP-2109  
FUNCTIO NAL BLO CK D IAGRAM  
SUMMARY  
16-Bit Fixed-Point DSP Microprocessors w ith  
On-Chip Mem ory  
Enhanced Harvard Architecture for Three-Bus  
Perform ance: Instruction Bus & Dual Data Buses  
Independent Com putation Units: ALU, Multiplier/  
Accum ulator, and Shifter  
MEMORY  
DATA ADDRESS  
GENERATORS  
PROGRAM  
SEQUENCER  
PROGRAM  
MEMORY  
DATA  
MEMORY  
DAG 2  
DAG 1  
EXTERNAL  
ADDRESS  
BUS  
PROGRAM MEMORY ADDRESS  
Single-Cycle Instruction Execution & Multifunction  
Instructions  
DATA MEMORY ADDRESS  
On-Chip Program Mem ory RAM or ROM  
& Data Mem ory RAM  
Integrated I/ O Peripherals: Serial Ports and Tim er  
PROGRAM MEMORY DATA  
DATA MEMORY DATA  
EXTERNAL  
DATA  
BUS  
FEATURES  
20 MIPS, 50 ns Maxim um Instruction Rate  
Separate On-Chip Buses for Program and Data Mem ory  
Program Mem ory Stores Both Instructions and Data  
(Three-Bus Perform ance)  
TIMER  
ARITHMETIC UNITS  
MAC SHIFTER  
SERIAL PORTS  
SPORT 0 SPORT 1  
ALU  
ADSP-2100 CORE  
Dual Data Address Generators w ith Modulo and  
Bit-Reverse Addressing  
Efficient Program Sequencing w ith Zero-Overhead  
Looping: Single-Cycle Loop Setup  
Autom atic Booting of On-Chip Program Mem ory from  
Byte-Wide External Mem ory (e.g., EPROM )  
Double-Buffered Serial Ports w ith Com panding Hardw are,  
Autom atic Data Buffering, and Multichannel Operation  
Three Edge- or Level-Sensitive Interrupts  
Low Pow er IDLE Instruction  
T he ADSP-2100 Family’s flexible architecture and compre-  
hensive instruction set support a high degree of parallelism.  
In one cycle the ADSP-2104/ADSP-2109 can perform all  
of the following operations:  
•
•
•
•
•
•
Generate the next program address  
Fetch the next instruction  
Perform one or two data moves  
Update one or two data address pointers  
Perform a computation  
Receive and transmit data via one or two serial ports  
PLCC Package  
GENERAL D ESCRIP TIO N  
T he ADSP-2104 and ADSP-2109 processors are single-chip  
microcomputers optimized for digital signal processing (DSP)  
and other high speed numeric processing applications. T he  
ADSP-2104/ADSP-2109 processors are built upon a common  
core. Each processor combines the core DSP architecture—  
computation units, data address generators, and program  
sequencer—with differentiating features such as on-chip  
program and data memory RAM (ADSP-2109 contains 4K  
words of program ROM), a programmable timer, and two  
serial ports.  
T he ADSP-2104 contains 512 words of program RAM, 256  
words of data RAM, an interval timer, and two serial ports.  
T he ADSP-2104L is a 3.3 volt power supply version of the  
ADSP-2104; it is identical to the ADSP-2104 in all other  
characteristics.  
T he ADSP-2109 contains 4K words of program ROM and  
256 words of data RAM, an interval timer, and two serial ports.  
T he ADSP-2109L is a 3.3 volt power supply version of the  
ADSP-2109; it is identical to the ADSP-2109 in all other  
characteristics.  
Fabricated in a high speed, submicron, double-layer metal  
CMOS process, the ADSP-2104/ADSP-2109 operates at  
20 MIPS with a 50 ns instruction cycle time. T he ADSP-2104L  
and ADSP-2109L are 3.3 volt versions which operate at  
13.824 MIPS with a 72.3 ns instruction cycle time. Every  
instruction can execute in a single cycle. Fabrication in CMOS  
results in low power dissipation.  
REV. 0  
Inform ation furnished by Analog Devices is believed to be accurate and  
reliable. However, no responsibility is assum ed by Analog Devices for its  
use, nor for any infringem ents of patents or other rights of third parties  
which m ay result from its use. No license is granted by im plication or  
otherwise under any patent or patent rights of Analog Devices.  
© Analog Devices, Inc., 1996  
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.  
Tel: 617/ 329-4700  
Fax: 617/ 326-8703  
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