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ADN2818 PDF预览

ADN2818

更新时间: 2024-01-03 13:49:06
品牌 Logo 应用领域
亚德诺 - ADI 时钟
页数 文件大小 规格书
35页 318K
描述
Continuous Rate 12.3Mb/s to 2.7Gb/s Clock and Data Recovery ICs

ADN2818 技术参数

是否无铅: 含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:QFN
包装说明:HVQCCN, LCC32,.2SQ,20针数:32
Reach Compliance Code:compliantECCN代码:5A991.B.3
HTS代码:8542.39.00.01风险等级:5.25
Is Samacsys:N应用程序:SONET;SDH
JESD-30 代码:S-XQCC-N32JESD-609代码:e3
长度:5 mm湿度敏感等级:3
功能数量:1端子数量:32
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:UNSPECIFIED封装代码:HVQCCN
封装等效代码:LCC32,.2SQ,20封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度(摄氏度):260
电源:3.3 V认证状态:Not Qualified
座面最大高度:1 mm子类别:ATM/SONET/SDH ICs
最大压摆率:0.217 mA标称供电电压:3.3 V
表面贴装:YES电信集成电路类型:ATM/SONET/SDH CLOCK RECOVERY CIRCUIT
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:40
宽度:5 mmBase Number Matches:1

ADN2818 数据手册

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Continuous Rate 12.3Mb/s to 2.7Gb/s  
Clock and Data Recovery ICs  
Preliminary Technical Data  
ADN2817/ADN2818  
FEATURES  
PRODUCT DESCRIPTION  
Serial data input: 12.3 Mb/s to 2.7 Gb/s  
Exceeds ITU-T Jitter Specifications  
The ADN2817/ADN2818 provides the receiver functions of  
quantization, signal level detect, and clock and data recovery for  
continuous data rates from 12.3 Mb/s to 2.7 Gb/s. The  
ADN2817/ADN2818 automatically locks to all data rates  
without the need for an external reference clock or  
programming. All SONET jitter requirements are exceeded,  
including jitter transfer, jitter generation, and jitter tolerance.  
All specifications are quoted for −40°C to +85°C ambient  
temperature, unless otherwise noted.  
Integrated Limiting Amp: 6mV sensitivity (ADN2817 only)  
Adjustable slice level: 100 mV (ADN2817 only)  
Patented dual-loop clock recovery architecture  
Programmable LOS detect (ADN2817 only)  
Slice level and sample phase adjustments (ADN2817 only)  
Integrated PRBS Generator and Detector  
No reference clock required  
Loss of lock indicator  
This device, together with a PIN diode and a TIA preamplifier,  
can implement a highly integrated, low cost, low power fiber  
optic receiver.  
Supports Double Data Rate  
Relative Bit Error Rate Monitor  
Rate Selectivity without the use of a reference clock  
I2C™ interface to access optional features  
Single-supply operation: 3.3 V  
Low power: 650/600 mW (ADN2817/ADN2818)  
5 mm × 5 mm 32-lead LFCSP  
The ADN2817/ADN2818 have many optional features available  
via an I2C interface, e.g. the user can read back the data rate that  
the ADN2817/ADN2818 is locked on to, or the user can set the  
device to only lock to one particular data rate if provisioning of  
data rates is required.  
APPLICATIONS  
SONET OC-1/3/12/48 and all associated FEC rates  
Fibre Channel, 2× Fibre Channel , GbE, HDTV, etc.  
WDM transponders  
The ADN2817/ADN2818 is available in a compact 5 mm × 5  
mm 32-lead chip scale package.  
Regenerators/repeaters  
Test equipment  
FUNCTIONAL  
BLOCK DIAGRAM  
REFCLKP/N  
(optional)  
VCC  
VEE  
LOL  
CF1  
CF2  
Freq/  
Lock  
Det  
Loop  
Filter  
Slice Adjust  
(ADN2817  
SLICEP/N  
only)  
PIN  
Phase  
Det.  
Phase  
Shifter  
Loop  
Filter  
VCO  
Σ
NIN  
VREF  
LOS Detect  
(ADN2817  
only)  
Data  
Re-Timing  
2
I C  
Registers  
THRADJ SDOUT DATAOUTP/N  
CLKOUTP/N  
SCK SDA  
Figure 1 ADN2817/ADN2818 Functional Block Diagram  
Rev.PrA  
Information furnished by Analog Devices is believed to be accurate and reliable.  
However, no responsibility is assumed by Analog Devices for its use, nor for any  
infringements of patents or other rights of third parties that may result from its use.  
Specifications subject to change without notice. No license is granted by implication  
or otherwise under any patent or patent rights of Analog Devices. Trademarks and  
registered trademarks are the property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Fax: 781.326.8703  
www.analog.com  
© 2006 Analog Devices, Inc. All rights reserved.  

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